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Volumn 7636, Issue , 2010, Pages

Full chip correction of EUV design

Author keywords

EUV; flare; OPC; scanner; shadowing effect

Indexed keywords

193-NM LITHOGRAPHY; ADVANCED MANUFACTURING; BIAS CORRECTION; CD MEASUREMENTS; DATA SETS; ELECTRONIC DESIGN AUTOMATION; EUV MASK; FEASIBILITY STUDIES; FEATURE SIZES; FULLY INTEGRATED; MODEL CALIBRATION; MODEL CALIBRATION AND VALIDATION; OPC MODELS; OPTICAL CORRECTIONS; OPTICAL PROXIMITY CORRECTIONS; PRE-PRODUCTION; SHADOWING EFFECTS; SHIN-ETSU; SPECIFIC EFFECTS; THROUGH PITCH; TWO-DIMENSIONAL STRUCTURES; WAFER LEVEL;

EID: 77953385575     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.846966     Document Type: Conference Paper
Times cited : (13)

References (9)
  • 6
    • 77952346796 scopus 로고    scopus 로고
    • Demonstration of scaled 0.099μm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology
    • A. Veloso et al., "Demonstration of scaled 0.099μm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology" IEEE International Electron Devices Meeting - IEDM (2009)
    • IEEE International Electron Devices Meeting - IEDM (2009)
    • Veloso, A.1
  • 7
    • 37149034956 scopus 로고    scopus 로고
    • Extreme ultraviolet lithography at IMEC: Shadowing compensation and flare mitigation strategy
    • G. F. Lorusso, A. M. Goethals, R. Jonckheere, J. Hermans, and K. Ronse, A. M. Myers, I. Kim, "Extreme ultraviolet lithography at IMEC: Shadowing compensation and flare mitigation strategy", J. Vac. Sci. Technol. B Volume 25, Issue 6, pp. 2127-2131 (2007)
    • (2007) J. Vac. Sci. Technol. B , vol.25 , Issue.6 , pp. 2127-2131
    • Lorusso, G.F.1    Goethals, A.M.2    Jonckheere, R.3    Hermans, J.4    Ronse, K.5    Myers, A.M.6    Kim, I.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.