DDMR: Dynamic and scalable dual modular redundancy with short validation intervals

IEEE Computer Architecture Letters

Volumn 7, Issue 2, 2008, Pages 65-68

  Golander, Amit ^a   Weiss, Shlomo ^a   Ronen, Ronny ^b  

^a TEL AVIV UNIVERSITY   (Israel)

^b INTEL CORPORATION   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

DOCKING; ERROR CORRECTION; ERROR DETECTION; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; QUALITY ASSURANCE; REDUNDANCY; RELIABILITY;

BANDWIDTH REQUIREMENTS; CMP ARCHITECTURES; DUAL MODULAR REDUNDANCIES; IN CHIPS; MINIMAL AREAS; MODULAR REDUNDANCIES; MULTICORE ARCHITECTURES; PARALLEL PROGRAMS; POWER RESOURCES; REDUNDANT PROCESSING; RING ARCHITECTURES; SOFT ERROR DETECTIONS; SOFT ERRORS;

MICROPROCESSOR CHIPS;

EID: 58149131807     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2008.12     Document Type: Article

References (9)

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