-
1
-
-
18144393357
-
Definitions of noise margin in logic systems
-
Sept.
-
C. F. Hill, "Definitions of noise margin in logic systems," Mullard Technology Communications, pp. 239-245, Sept. 1967.
-
(1967)
Mullard Technology Communications
, pp. 239-245
-
-
Hill, C.F.1
-
2
-
-
0017980692
-
Static and dynamic noise margins of logic circuits
-
J. Lohstroh, "Static and dynamic noise margins of logic circuits," IEEE Journal of Solid-State Circuits, vol. 14, pp. 591-598, 1979.
-
(1979)
IEEE Journal of Solid-State Circuits
, vol.14
, pp. 591-598
-
-
Lohstroh, J.1
-
4
-
-
33750815896
-
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
-
Jan. 1
-
E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies," IEEE Journal of Solid-State Circuits, Jan. 1, 2006.
-
(2006)
IEEE Journal of Solid-State Circuits
-
-
Grossar, E.1
Stucchi, M.2
Maex, K.3
Dehaene, W.4
-
5
-
-
55349085115
-
Analyzing N-Curve Metrics for Sub- Threshold 65nm CMOS SRAM
-
Jan. 1
-
M. Samson and M. B. Srinivas, "Analyzing N-Curve Metrics for Sub- Threshold 65nm CMOS SRAM," Nanotechnology, Jan. 1, 2008.
-
(2008)
Nanotechnology
-
-
Samson, M.1
Srinivas, M.B.2
-
7
-
-
70349299081
-
A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-κ Metal-Gate CMOS with Integrated Power Management
-
Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. Ng, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, "A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-κ Metal-Gate CMOS with Integrated Power Management," in International Solid State Circuits Conference, 2009, pp. 456-458.
-
International Solid State Circuits Conference, 2009
, pp. 456-458
-
-
Wang, Y.1
Bhattacharya, U.2
Hamzaoglu, F.3
Kolar, P.4
Ng, Y.5
Wei, L.6
Zhang, Y.7
Zhang, K.8
Bohr, M.9
-
8
-
-
46149119897
-
Analytical Modeling of SRAM Dynamic Stability
-
Z. Bin, A. Arapostathis, S. Nassif, and M. Orshansky, "Analytical Modeling of SRAM Dynamic Stability," in IEEE/ACM International Conference on Computer-Aided Design, 2006, pp. 315-322.
-
IEEE/ACM International Conference on Computer-Aided Design, 2006
, pp. 315-322
-
-
Bin, Z.1
Arapostathis, A.2
Nassif, S.3
Orshansky, M.4
-
9
-
-
0020906578
-
Worst-case static noise margin criteria for logic circuits and their mathematical equivalence
-
J. Lohstroh, E. Seevinck, and J. de Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE Journal of Solid-State Circuits, vol. 18, pp. 803-807, 1983.
-
(1983)
IEEE Journal of Solid-State Circuits
, vol.18
, pp. 803-807
-
-
Lohstroh, J.1
Seevinck, E.2
De Groot, J.3
-
10
-
-
0027695492
-
Noise margin criteria for digital logic circuits
-
Nov. 1
-
J. R. Hauser, "Noise margin criteria for digital logic circuits," IEEE Transactions on Education, vol. 36, pp. 363 - 368, Nov. 1, 1993.
-
(1993)
IEEE Transactions on Education
, vol.36
, pp. 363-368
-
-
Hauser, J.R.1
-
11
-
-
51349100877
-
Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch
-
G. M. Huang, W. Dong, Y. Ho, and P. Li, "Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch," Behavioral Modeling and Simulation Workshop, Jan. 1, 2007.
-
Behavioral Modeling and Simulation Workshop, Jan. 1, 2007
-
-
Huang, G.M.1
Dong, W.2
Ho, Y.3
Li, P.4
-
12
-
-
57849163592
-
SRAM dynamic stability: Theory, variability and analysis
-
W. Dong, P. Li, and G. M. Huang, "SRAM dynamic stability: Theory, variability and analysis," International Conference on Computer-Aided Design, Jan. 1, 2008.
-
International Conference on Computer-Aided Design, Jan. 1, 2008
-
-
Dong, W.1
Li, P.2
Huang, G.M.3
-
13
-
-
57549111680
-
Analyzing static and dynamic write margin for nanometer SRAMs
-
Jan. 1
-
J. Wang, S. Nalam, and B. H. Calhoun, "Analyzing static and dynamic write margin for nanometer SRAMs," ISLPED, Jan. 1, 2008.
-
(2008)
ISLPED
-
-
Wang, J.1
Nalam, S.2
Calhoun, B.H.3
-
15
-
-
51749104874
-
Portless SRAM - A High- Performance Alternative to the 6T Methodology
-
M. Wieckowski, S. Patil, and M. Margala, "Portless SRAM - A High- Performance Alternative to the 6T Methodology," IEEE Journal of Solid- State Circuits, vol. 42, pp. 2600-2610, 2007.
-
(2007)
IEEE Journal of Solid- State Circuits
, vol.42
, pp. 2600-2610
-
-
Wieckowski, M.1
Patil, S.2
Margala, M.3
-
16
-
-
50249167238
-
Yield-driven near-threshold SRAM design
-
G. K. Chen, D. Blaauw, T. Mudge, D. Sylvester, and K. Nam Sung, "Yield-driven near-threshold SRAM design," in International Conference on Computer-Aided Design, 2007, pp. 660-666.
-
International Conference on Computer-Aided Design, 2007
, pp. 660-666
-
-
Chen, G.K.1
Blaauw, D.2
Mudge, T.3
Sylvester, D.4
Nam Sung, K.5
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