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Volumn , Issue , 2010, Pages 795-800

A black box method for stability analysis of arbitrary SRAM cell structures

Author keywords

Dynamic noise margin; Memory; Robustness; Stability; Static noise margin

Indexed keywords

CONVERGENCE OF NUMERICAL METHODS; CURVE FITTING; CYTOLOGY; DATA STORAGE EQUIPMENT; FAILURE ANALYSIS; IMPORTANCE SAMPLING; ROBUSTNESS (CONTROL SYSTEMS); STABILITY; STATIC RANDOM ACCESS STORAGE;

EID: 77953096884     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5456943     Document Type: Conference Paper
Times cited : (24)

References (16)
  • 1
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  • 2
    • 0017980692 scopus 로고
    • Static and dynamic noise margins of logic circuits
    • J. Lohstroh, "Static and dynamic noise margins of logic circuits," IEEE Journal of Solid-State Circuits, vol. 14, pp. 591-598, 1979.
    • (1979) IEEE Journal of Solid-State Circuits , vol.14 , pp. 591-598
    • Lohstroh, J.1
  • 5
    • 55349085115 scopus 로고    scopus 로고
    • Analyzing N-Curve Metrics for Sub- Threshold 65nm CMOS SRAM
    • Jan. 1
    • M. Samson and M. B. Srinivas, "Analyzing N-Curve Metrics for Sub- Threshold 65nm CMOS SRAM," Nanotechnology, Jan. 1, 2008.
    • (2008) Nanotechnology
    • Samson, M.1    Srinivas, M.B.2
  • 9
    • 0020906578 scopus 로고
    • Worst-case static noise margin criteria for logic circuits and their mathematical equivalence
    • J. Lohstroh, E. Seevinck, and J. de Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE Journal of Solid-State Circuits, vol. 18, pp. 803-807, 1983.
    • (1983) IEEE Journal of Solid-State Circuits , vol.18 , pp. 803-807
    • Lohstroh, J.1    Seevinck, E.2    De Groot, J.3
  • 10
    • 0027695492 scopus 로고
    • Noise margin criteria for digital logic circuits
    • Nov. 1
    • J. R. Hauser, "Noise margin criteria for digital logic circuits," IEEE Transactions on Education, vol. 36, pp. 363 - 368, Nov. 1, 1993.
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    • Hauser, J.R.1
  • 13
    • 57549111680 scopus 로고    scopus 로고
    • Analyzing static and dynamic write margin for nanometer SRAMs
    • Jan. 1
    • J. Wang, S. Nalam, and B. H. Calhoun, "Analyzing static and dynamic write margin for nanometer SRAMs," ISLPED, Jan. 1, 2008.
    • (2008) ISLPED
    • Wang, J.1    Nalam, S.2    Calhoun, B.H.3
  • 15
    • 51749104874 scopus 로고    scopus 로고
    • Portless SRAM - A High- Performance Alternative to the 6T Methodology
    • M. Wieckowski, S. Patil, and M. Margala, "Portless SRAM - A High- Performance Alternative to the 6T Methodology," IEEE Journal of Solid- State Circuits, vol. 42, pp. 2600-2610, 2007.
    • (2007) IEEE Journal of Solid- State Circuits , vol.42 , pp. 2600-2610
    • Wieckowski, M.1    Patil, S.2    Margala, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.