High-throughput layered LDPC decoding architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 4, 2009, Pages 582-587

  Cui, Zhiqiang ^a   Wang, Zhongfeng ^b   Liu, Youjian ^c  

^a QUALCOMM INC   (United States)

^b BROADCOM CORPORATION   (United States)

^c University of Colorado at Boulder   (United States)

Author keywords

Decoder; Error correction codes; Low density parity check (LDPC); Quasi cyclic (QC) codes; VLSI architecture

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); ERROR CORRECTION; ITERATIVE DECODING; QUANTUM THEORY;

DECODER; ERROR CORRECTION CODES; LOW-DENSITY PARITY-CHECK (LDPC); QUASI-CYCLIC (QC) CODES; VLSI ARCHITECTURE;

CODES (SYMBOLS);

EID: 62949127873     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2005308     Document Type: Article

References (13)

1. R. G. Gallager, "Low-density parity-check codes," IRE Trans. Inf. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
2. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity check code decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
3. A. Darabiha, A. C. Carusone, and F. R. Kschischang, "Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity," in Proc. ISCAS, May 2005, vol. 5, pp. 5194-5197.
4. C. Lin, K. Lin, H. Chang, and C. Lee, "A 3.33 Gb/s (1200, 720) low-density parity check code decoder," in Proc. ESSCIRC, Sep. 2005, pp. 211-214.
5. J. Sha, M. Gao, Z. Zhang, L. Li, and Z. Wang, "Efficient decoder implementation for QC-LDPC codes," in Proc. ICCCAS, Jun. 2006, vol. 4, pp. 2498-2502.
6. K. K. Gunnam, G. S. Choi, and M. B. Yeary, "A parallel VLSI architecture for layered decoding for array LDPC codes," in Proc. VLSID, Jan. 2007, pp. 738-73.
7. E. Sharon, S. Litsyn, and J. Goldberger, "An efficient message-passing schedule for LDPC decoding," in Proc. 23rd IEEE Convention Elect. Electron. Eng. Israel, Sep. 2004, pp. 223-226.
8. D. E. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," in Proc. IEEE Workshop Signal Process. Syst., 2004, pp. 107-112.
9. L. Chen, J. Xun, I. Djurdjevic, and S. Lin, "Near shannon limit quasi- cyclic low-density parity-check codes," IEEE Trans. Commun., vol. 52, no. 7, pp. 1038-1042, Jul. 2004.
10. Y. Zhang, W. E. Ryan, and Y. Li, "Structured eIRA codes with low floors," in Proc. Int. Symp. Inf. Theory, Sep. 2005, pp. 174-178.
11. Z. Wang and Z. Cui, "A memory efficient partially parallel decoder architecture for QC-LDPC codes," in Proc. 39th Asilomar Conf. Signals, Syst. Comput., 2005, pp. 729-733.
12. H. Xiao-Yu, E. Eleftheriou, and D. M. Arnold, "Regular and irregular progressive edge-growth tanner graphs," IEEE Trans. Inf. Theory, vol. 51, no. 1, pp. 386-398, Jan. 2005.
13. J. Zhang and M. P. C. Fossorier, "Shuffled iterative decoding," IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005.