Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies

EuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems

Volumn , Issue , 2008, Pages

  Vandevelde, Bart ^a   Okoro, Chukwudi ^a   Gonzalez, Mario ^a   Swinnen, Bart ^a   Beyne, Eric ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; IC PACKAGING; INTERNATIONAL CONFERENCES; MECHANICAL RELIABILITY; MICRO-SYSTEMS; MINIATURISATION; MULTI-PHYSICS SIMULATION; THERMAL RESISTANCE; WAFER LEVELS;

ELECTRONICS INDUSTRY; EXPERIMENTS; IMPACT RESISTANCE; MICROELECTRONICS; SPEED;

SILICON CARBIDE;

EID: 49249089484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2008.4525106     Document Type: Conference Paper

References (11)

1. E Beyne, 4th International Symposium on Microelectronics and packaging, pp. 25-34, ISMP2005, Seoul, Korea, September 28-29, 2005.
2. P. Garrou, 3D-integration: a status report, proceedings "3D Architectures for semiconductor integration and packaging"n RTI international, Burlingame, Tempe, Arizona, June 13-15, 2005.
3. S. List, The third dimension: fact or fiction, "3D Architectures for semiconductor integration and packaging"n RTI international, Burlingame, Tempe, Arizona, June 13-15, 2005.
4. th International Electronics Manufacturing Technology Symposium, July 2004, pp. 64-67.
5. L. C. Chen, B. Vandevelde, B. Swinnen, E. Beyne, Enabling SPICE-type modeling of the thermal properties of 3D-stacked IC's, Proceedings of Electronics Packaging Technology Conference, missing publisher, Singapore, pp.492-499, Dec. 2006.
6. C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde, Thermal cycle reliability of 3D chip stacked package using Pb-free solder bumps: parameter study by FEM analysis, 7th Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems - EuroSimE, IEEE, Como, Italy, pp.237-242, Apr. 2006.
7. C. Okoro, G. Eneman, M. Gonzalez, B. Vandevelde, B. Swinnen, S. Stoukatch, E. Beyne, D. Vandepitte, Analysis of the induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-throughvias in 3D-SIC architecture, Proceedings 57th Electronic Components and Technology Conference - ECTC, IEEE, New Jersey, USA, pp.249-255, May. 2007.
8. M. Gonzalez, R. Labie, B. Vandevelde, E. Beyne, Influence of dielectric materials and via geometry on the thermomechanical behavior of silicon through interconnects, 10th Annual SMTA Pan Pacific Microelectronics Symposium & Exhibition, SMTA, Kauai, HI, USA, pp.9-14, Jan. 2005.
9. I. Francois; S. Tezcan Deniz; C. Teixeira Ricardo; Soussan Philippe; Baert Kris, "3D Embedding and Interconnection of Ultra Thin (< 20 μm) Silicon Dies", EPTC 2007, 10-12 December 2007, Singapore (accepted)
10. B.Swinnen, W.Ruythooren, P.De Moor, L.Bogaerts, L.Carbonell, K.De Munck, B.Eyckens, S.Stoukatch, D.Sabuncuoglu Tezcan, Z.Tokei, J.Vaes, J.Van Aelst, E.Beyne, "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias", "International Electron Devices Meeting - IEDM. Technical Digest", IEEE, San Francisco, CA, USA, Dec. 2006.
11. Matsuda K., et al "Nonlinear piezoresistance effects in Silicon" J. Appl. Phys. Vol. 73, No. 4, Feb. 1993, pp. 1838-1846.