Non-uniform power access in large caches with low-swing wires

16th International Conference on High Performance Computing, HiPC 2009 - Proceedings

Volumn , Issue , 2009, Pages 59-68

  Udipi, Aniruddha N ^a   Muralimanohar, Naveen ^b   Balasubramonian, Rajeev ^a  

^a UNIVERSITY OF UTAH   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE ACCESS; CHIP AREAS; COMPLEX INTERCONNECTS; DYNAMIC POWER; ENERGY CONSUMPTION; ENERGY-SAVING MEASURES; LOW SWING; MODERN PROCESSORS; NETWORK POWER; NONUNIFORM; ON-CHIP NETWORKS; PERFORMANCE TRADE-OFF; PROCESSOR POWER;

WIRE;

MACHINE DESIGN;

EID: 77952135865     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HIPC.2009.5433222     Document Type: Conference Paper

References (25)

1. C. McNairy and R. Bhatia, "Montecito: A Dual-Core, Dual-Thread Itanium Processor," IEEE Micro, vol. 25(2), March/April 2005.
2. "First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehalem)," Intel Whitepaper, Tech. Rep., 2008.
3. C. Kim, D. Burger, and S. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches," in Proceedings of ASPLOS, 2002.
4. N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0," in Proceedings of MICRO, 2007.
5. N. Muralimanohar and R. Balasubramonian, "Interconnect Design Considerations for Large NUCA Caches," in Proceedings of ISCA, 2007.
6. "CACTI: An Integrated Cache and Memory Access Time, Cycle Time, Area, Leakage, and Dynamic Power Model," http://www.hpl.hp.com/research/ cacti/.
7. "High-k and Metal Gate Research," http://www.intel.com/ technology/silicon/high-k.htm.
8. S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Benoit, R. Varada, J. Leung, R. Lim, and S. Vora, "A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cache," IEEE Journal of Solid State Circuits, vol. 42, no. 1, pp. 17-25, January 2007.
9. K. Zhang, U. Bhattacharya, Z. Chen, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction Scheme," in Proceedings of VLSI, 2004.
10. S. Heo, K. Barr, M. Hampton, and K. Asanovic, "Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines," in Proceedings of ISCA, 2002.
11. K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge, "Drowsy Caches: Simple Techniques for Reducing Leakage Power," in Proceedings of ISCA, 2002.
12. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," in Proceedings of ISCA, 2001.
13. S. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar, "An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep Submicron High-Performance I-Caches," in Proceedings of HPCA, 2001.
14. R. Ho, "On-Chip Wires: Scaling and Efficiency," Ph.D. dissertation, Stanford University, August 2003.
15. R. Ho, K. Mai, and M. Horowitz, "Efficient On-Chip Global Interconnects," in Proceedings of VLSI, 2003.
16. K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, and M. Horowitz, "Architecture and Circuit Techniques for a Reconfigurable Memory Block," in Proceedings of ISSCC, 2004.
17. K. Mai, T. Paaske, N. Jaysena, R. Ho, W. J. Dally, and M. Horowitz, "Smart Memories: A Modular Reconfigurable Architecture," in Proceedings of ISCA, 2000.
18. J. Kin, M. Gupta, and W. H. Mangione-Smith, "The Filter Cache: An Energy Efficient Memory Structure," in Proceedings of MICRO, 1997.
19. D. Burger and T. Austin, "The Simplescalar Toolset, Version 2.0," University of Wisconsin-Madison, Tech. Rep. TR-97-1342, June 1997.
20. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically Characterizing Large Scale Program Behavior," in Proceedings of ASPLOS, 2002.
21. K. Banerjee and A. Mehrotra, "A Power-optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs," IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 2001-2007, November 2002.
22. R. Ho, T. Ono, F. Liu, R. Hopkins, A. Chow, J. Schauer, and R. Drost, "High-speed and low-energy capacitively-driven on-chip wires," in Proceedings of ISSCC, 2007.
23. A. Agarwal, H. Li, and K.Roy, "DRG-Cache: A Data Retention Gated-Ground Cache for Low Power," in Proceedings of the 39th Conference on Design Automation, June 2002.
24. C.-L. Yang and C.-H. Lee, "HotSpot Cache: Joint Temporal and Spatial Location Exploitation for I-cache Energy Reduction," in Proceedings of ISLPED, 2004.
25. T. Ishihara and F. Fallah, "A Non-Uniform Cache Architecture for Low Power System Design," in Proceedings of ISLPED, 2005.