Fuzzy neural network based yield prediction model for semiconductor manufacturing system

International Journal of Production Research

Volumn 48, Issue 11, 2010, Pages 3225-3243

  Wu, Lihui ^a   Zhang, Jie ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

Fuzzy neural networks; Prediction; Semiconductor manufacturing system; Yield

Indexed keywords

ELECTRICAL TESTS; EXPERIMENTAL DATA; IMPACT FACTOR; INDEPENDENT VARIABLES; PREDICTION; PREDICTION ACCURACY; SEMICONDUCTOR FABRICATION LINES; SEMICONDUCTOR MANUFACTURING INDUSTRY; SEMICONDUCTOR MANUFACTURING SYSTEMS; YIELD PREDICTION; YIELD PREDICTION MODELS;

DIES; FORECASTING; MANUFACTURE; MATHEMATICAL MODELS;

FUZZY NEURAL NETWORKS;

EID: 77951099774     PISSN: 00207543     EISSN: 1366588X     Source Type: Journal    
DOI: 10.1080/00207540902795307     Document Type: Article

References (24)

1. Aakash, T. and Bayoumi, M.A., 1992. Defect clustering viewed through generalised Poisson distribution. IEEE Transactions on Semiconductor Manufacturing, 5 (3), 196-206.
2. Chen, T. and Lin, Y.C., 2008. A fuzzy-neural system incorporating unequally important expert opinions for semiconductor yield forecasting. International Journal of Uncertainty. Fuzziness and Knowledge-Based Systems, 16 (1), 35-58.
3. Chen, T. and Wang, M.J., 1999. A fuzzy set approach for yield learning modeling in wafer manufacturing. IEEE Transactions on Semiconductor Manufacturing, 12 (2), 252-258.
4. Chung, K.S. and Sang, C.P., 2000. A machine learning approach to yield management in semiconductor manufacturing. International Journal of Production Research, 38 (17), 4261-4271.
5. Cunningham, J.A., 1990. The use and evaluation of yield models in integrated circuit manufacturing. IEEE Transactions on Semiconductor Manufacturing, 3 (2), 60-71.
6. Cunningham, S.P. and Spanos, C.J., 1995. Semiconductor yield improvement: results and best practices. IEEE Transactions on Semiconductor Manufacturing, 8 (2), 103-109.
7. Friedman, D.J., et al., 1997. Model-free estimation of defect clustering in integrated circuit fabrication. IEEE Transactions on Semiconductor Manufacturing, 10 (3), 344-359.
8. Gurnani, H., Anupindi, R. and Akella, R., 1992. Control of batch processing systems in semiconductor wafer fabrication facilities. IEEE Transactions on Semiconductor Manufacturing, 5 (4), 319-328.
9. Jun, C.-H., et al., 1999. A simulation-based semiconductor chip yield model incorporating a new defect cluster index. Microelectronics Reliability, 39, 451-456.
10. Kim, T.S., et al., 2000. Yield prediction models for optimisation of high-speed micro-processor manufacturing processes. 26th IEEE/CPMT international electronics manufacturing technology symposium, 2-3 October 2000, Santa Clara, CA, USA. Piscataway, NJ: IEEE, 368-373.
11. Kim, T.S., 2002. Intelligent yield and speed prediction models for high-speed microprocessors. IEEE electronic components and technology conference, 28-31 May 2002, San Diego, CA, USA. Piscataway, NJ: IEEE, 1158-1162.
12. Koren, I., Koren, Z., and Stepper, C.H., 1993. A unified negative binomial distribution for yield analysis of defect-tolerant circuits. IEEE Transactions on Computers, 42, 724-734.
13. Kumar, N., et al., 2006. A review of yield modeling techniques for semiconductor manufacturing. International Journal of Production Research, 44 (23), 5019-5036.
14. Langford, R.E., Liou, J.J., and Raghavan, V., (2001). The application and validation of a new robust windowing method for the Poisson yield model. Advanced semiconductor manufacturing conference, IEEE/SEMI, 23-24 April 2001, Munich, Germany. Piscataway, NJ: IEEE, 157-160.
15. Leachman, R.C., 1993. The competitive semiconductor manufacturing survey. IEEE international symposium on semiconductor manufacturing conference, 20-21 September 1993, Austin, Texas, USA. Piscataway, NJ: IEEE, 359-381.
16. Okabe, T., Nagata, M., and Shimada, S., 1972. Analysis on yield of integrated circuit and a new expression of the yield. Electrical Engineering in Japan, 92 (12), 135-141.
17. Rumelhart, D.E. and McClelland, J.L., 1989. Parallel distributed processing explorations in the mircostructure of cognition. Vol.1, Cambridge, MA: MIT Press.
18. Stapper, C.H., 1973. Defect density distribution for LSI yield calculations. IEEE Transaction Electron Devices (Correspondence), 20 (7), 655-657.
19. Stapper, C.H., 1976. LSI yield modeling and process monitoring. IBM Journal of Research and Development, 20 (3), 228-234.
20. Tong, L.-I., Lee, W.-I., and Su, C.-T., 1997. Using a neural network-based approach to predict the wafer yield in integrated circuit manufacturing. IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part C, 20 (4), 288-294.
21. Tong, L.-I. and Chao, L.-C., 2008. Novel yield model for integrated circuit with clustered defects. Expert Systems with Applications, 34, 2334-2341.
22. Uzsoy, R., et al., 1992. A review of production planning and scheduling models in the semiconductor industry. Part I: System characteristics, performance evaluation and production planning [J]. IIE Transactions, 24 (4), 47-60.
23. Uzsoy, R., et al., 1994. A review of production planning and scheduling models in the semiconductor industry. Part II: Shop-floor control [J]. IIE Transactions, 26 (5), 44-55.
24. Wong, A.Y., 1996. A statistical parametric and probe yield analysis methodology [C]. Proceedings of IEEE international symposium on defect and fault tolerance in VLSI systems, 6-8 November 1996, Boston, MA, USA. Los Alamitos, CA: IEEE Comput. Soc. Press, 131-139.