The application and validation of a new robust windowing method for the poisson yield model

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn 2, Issue , 2001, Pages 157-160

  Langford, Rick E ^a   Liou, Juin J ^b   Raghavan, Venkat ^c  

^a Agere Systems   (Singapore)

^b UNIVERSITY OF CENTRAL FLORIDA   (United States)

^c AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLEAN ROOMS; DATA REDUCTION; MICROPROCESSOR CHIPS; PROBABILITY; RANDOM PROCESSES;

POISSON YIELD MODEL; WINDOWING METHOD;

WSI CIRCUITS;

EID: 0035182907     PISSN: 1523553X     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASMC.2001.925640     Document Type: Article

References (3)

1. Large-area fault clusters and fault tolerance in VLSI circuits: A review
2. Circuit fabrication processes for spatially clustered defects
3. Statistical micro yield modeling