Intelligent yield and speed prediction models for high-speed microprocessors

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1158-1162

  Kim, Tae Seon ^a  

^a The Catholic University of Korea   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPROPAGATION; ELECTRONICS PACKAGING; NEURAL NETWORKS; REGRESSION ANALYSIS; WSI CIRCUITS;

ROOT MEAN SQUARE (RMS) ERROR;

MICROPROCESSOR CHIPS;

EID: 0036297067     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Semiconductor yield improvement: Results and best practices
2. On the assumption contained in semiconductor yield models
3. Advantages of plasma etch modeling using neural networks over statistical techniques
4. Using neural network process models to perform PECVD silicon dioxide recipe synthesis via genetic algorithms
5. Statistical experimental design for MBE process characterization
6. Sequential modeling of via formation in photosensitive dielectric materials for MCM-D applications
7. Intelligent yield prediction models for high-speed microprocessors
8. A review of statistical tool set for the yield enhancement of integrated circuits
9. A statistical parametric and probe yield analysis methodology
10. DOE/Opt: A system for design of experiments, response surface modeling, and optimization using process and device simulation
11. Manufacturing ICs the neural way
12. Calculating parametric yield limits