-
2
-
-
0025433611
-
The use and evaluation of yield models in integrated circuit manufacturing
-
May
-
J. A. Cunningham, "The use and evaluation of yield models in integrated circuit manufacturing," IEEE Trans. Semiconduct. Manufact., vol. 3, pp. 60-71, May 1990.
-
(1990)
IEEE Trans. Semiconduct. Manufact.
, vol.3
, pp. 60-71
-
-
Cunningham, J.A.1
-
3
-
-
0017982768
-
Yield-area analysis: Part I - A diagnostic tool for fundamental integrated circuit process problems
-
W. E. Ham, "Yield-area analysis: Part I - A diagnostic tool for fundamental integrated circuit process problems," RCA Rev., vol. 39, pp. 231-249, 1978.
-
(1978)
RCA Rev.
, vol.39
, pp. 231-249
-
-
Ham, W.E.1
-
4
-
-
0031200533
-
Monitoring wafer map data from integrated circuit fabrication processes for spatially clustered defects
-
in press
-
M. H. Hansen, V. N. Nair, and D. J. Friedman, "Monitoring wafer map data from integrated circuit fabrication processes for spatially clustered defects," Technometrics, vol. 39, no. 3, 1997, in press.
-
(1997)
Technometrics
, vol.39
, Issue.3
-
-
Hansen, M.H.1
Nair, V.N.2
Friedman, D.J.3
-
5
-
-
0019576202
-
Poisson process and integrated circuit yield problems
-
R. S. Hemmert, "Poisson process and integrated circuit yield problems," Solid-State Electron., vol. 24, no. 6, pp. 511-515, 1981.
-
(1981)
Solid-State Electron.
, vol.24
, Issue.6
, pp. 511-515
-
-
Hemmert, R.S.1
-
6
-
-
0028454905
-
A statistical study of defect maps of large area VLSI IC's
-
I. Koren, Z. Koren, and C. H. Stapper, "A statistical study of defect maps of large area VLSI IC's," IEEE Trans. VLSI Syst., vol. 2, no. 2, pp. 251-256, 1994.
-
(1994)
IEEE Trans. VLSI Syst.
, vol.2
, Issue.2
, pp. 251-256
-
-
Koren, I.1
Koren, Z.2
Stapper, C.H.3
-
8
-
-
0020844948
-
Spatial yield analysis in integrated circuit manufacture
-
Nov.
-
C. L. Mallory, D. S. Perloff, T. F. Hasan, and R. M. Stanley, "Spatial yield analysis in integrated circuit manufacture," Solid State Technol., pp. 121-127, Nov. 1983.
-
(1983)
Solid State Technol.
, pp. 121-127
-
-
Mallory, C.L.1
Perloff, D.S.2
Hasan, T.F.3
Stanley, R.M.4
-
9
-
-
0000975370
-
The interpretation of statistical maps
-
P. A. P. Moran, "The interpretation of statistical maps," J. Roy. Stat. Soc. B, vol. 10, pp. 243-251, 1948.
-
(1948)
J. Roy. Stat. Soc. B
, vol.10
, pp. 243-251
-
-
Moran, P.A.P.1
-
10
-
-
84938162176
-
Cost-size optima of monolithic integrated circuits
-
B. T. Murphy, "Cost-size optima of monolithic integrated circuits," Proc. IEEE, vol. 52, pp. 1537-1545, 1964.
-
(1964)
Proc. IEEE
, vol.52
, pp. 1537-1545
-
-
Murphy, B.T.1
-
11
-
-
0015423592
-
Analysis of yield of integrated circuits and a new expression for the yield
-
T. Okabe, M. Nagata, and S. Shimada, "Analysis of yield of integrated circuits and a new expression for the yield," Electr. Eng. Jpn., vol. 92, pp. 135-141, 1972.
-
(1972)
Electr. Eng. Jpn.
, vol.92
, pp. 135-141
-
-
Okabe, T.1
Nagata, M.2
Shimada, S.3
-
12
-
-
0017544583
-
Modification of Poisson statistics: Modeling defects induced by diffusion
-
O. Paz and T. Lawson, "Modification of Poisson statistics: Modeling defects induced by diffusion," IEEE J. Solid-State Circuits, vol. SC-12, pp. 540-546, 1977.
-
(1977)
IEEE J. Solid-State Circuits
, vol.SC-12
, pp. 540-546
-
-
Paz, O.1
Lawson, T.2
-
14
-
-
0010968585
-
Defect density distribution for LSI yield calculations
-
C. H. Stapper, "Defect density distribution for LSI yield calculations," IEEE Trans. Electron Devices, vol. ED-20, pp. 655-657, 1973.
-
(1973)
IEEE Trans. Electron Devices
, vol.ED-20
, pp. 655-657
-
-
Stapper, C.H.1
-
15
-
-
0004744726
-
LSI yield modeling and process monitoring
-
_, "LSI yield modeling and process monitoring," IBM J. Res. Develop., vol. 20, pp. 228-234, 1976.
-
(1976)
IBM J. Res. Develop.
, vol.20
, pp. 228-234
-
-
-
16
-
-
0021782318
-
The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions
-
_, "The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions," IBM J. Res. Develop., vol. 29, no. 1, pp. 87-97, 1985.
-
(1985)
IBM J. Res. Develop.
, vol.29
, Issue.1
, pp. 87-97
-
-
-
17
-
-
0024629198
-
Large-area fault clusters and fault tolerance in VLSI circuits: A review
-
_, "Large-area fault clusters and fault tolerance in VLSI circuits: A review," IBM J. Res. Develop., vol. 33, no. 2, 1989.
-
IBM J. Res. Develop.
, vol.33
, Issue.2
, pp. 1989
-
-
-
18
-
-
0027591382
-
Detecting spatial effects from factorial experiments: An application in integrated-circuit manufacturing
-
W. Taam and M. Hamada, "Detecting spatial effects from factorial experiments: An application in integrated-circuit manufacturing," Technometrics, vol. 35, pp. 149-160, 1993.
-
(1993)
Technometrics
, vol.35
, pp. 149-160
-
-
Taam, W.1
Hamada, M.2
-
19
-
-
0019636930
-
A note on IC-yield statistics
-
R. M. Warner, "A note on IC-yield statistics," Solid-State Electronics, vol. 24, no. 11, pp. 1045-1047, 1981.
-
(1981)
Solid-State Electronics
, vol.24
, Issue.11
, pp. 1045-1047
-
-
Warner, R.M.1
-
20
-
-
0009418379
-
Some graphical methods in the analysis of spatial point patterns
-
V. Bartlett, Ed. New York: Wiley
-
P. J. Diggle, Some graphical methods in the analysis of spatial point patterns," in Interpreting Multivariate Data, V. Bartlett, Ed. New York: Wiley, 1981, pp. 55-73.
-
(1981)
Interpreting Multivariate Data
, pp. 55-73
-
-
Diggle, P.J.1
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