Bias-and-input interchanging technique for cyclic/pipelined ADCs with opamp sharing

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 57, Issue 3, 2010, Pages 168-172

  Kuo, Chun Hsien ^a   Kuo, Tai Haur ^a   Wen, Kow Liang ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b DeAmmonification Research Institute Co   (Taiwan)

Author keywords

Analog to digital converter (ADC); Low power; Low voltage; Opamp sharing

Indexed keywords

FINITE DIFFERENCE METHOD; OPERATIONAL AMPLIFIERS;

ANALOG TO DIGITAL CONVERTERS; DRIVING CIRCUITS; FULLY DIFFERENTIAL; LOW POWER; LOW VOLTAGES; PROOF OF CONCEPT; PSEUDO DIFFERENTIAL; SHARING ARCHITECTURES;

ANALOG TO DIGITAL CONVERSION;

EID: 77950296807     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2041815     Document Type: Article

References (14)

1. C.-H. Kuo and T.-H. Kuo, "Capacitor-swapping cyclic A/D conversion techniques with reduced mismatch sensitivity," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.55, no.12, pp. 1219-1223, Dec. 2008.
2. D.-Y. Chang, "Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.51, no.11, pp. 2123-2132, Nov. 2004.
3. Y.-D. Jeon, S.-C. Lee, K.-D. Kim, J.-K. Kwon, and J. Kim, "A 4.7 mW 0.32 mm2 10 b 30 MS/s pipelined ADC without a front-end S/H in 90 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 456-615.
4. J. Li, X. Zeng, L. Xie, J. Chen, J. Zhang, and Y. Guo, "A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications," IEEE J. Solid-State Circuits, vol.43, no.2, pp. 321-329, Feb. 2008.
5. Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2139-2151, Dec. 2004.
6. M. Waltari and K. A. I. Halonen, "1-V 9-bit pipelined switched-opamp ADC," IEEE J. Solid-State Circuits, vol.36, no.1, pp. 129-134, Jan. 2001.
7. H.-C. Kim, D.-K. Jeong, and W. Kim, "A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I, Reg. Papersfs, vol.53, no.4, pp. 795-801, Apr. 2006.
8. K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers," IEEE J. Solid State Circuits, vol.32, no.3, pp. 312-320, Mar. 1997.
9. B.-M. Min, P. Kim, F. W. Bowman, III, D. M. Boisvert, and A. J. Aude, "A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol.38, no.12, pp. 2031-2039, Dec. 2003.
10. P. C. Yu and H.-S. Lee, "2.5-V, 12-b, 5-Msamples/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol.31, no.12, pp. 1854-1861, Dec. 1996.
11. S.-T. Ryu, B.-S. Song, and K. Bacrania, "A 10-bit 50-MS/s pipelined ADC with opamp current reuse," IEEE J. Solid-State Circuits, vol.42, no.3, pp. 475-485, Mar. 2007.
12. D. Miyazaki, S. Kawahito, and M. Furuta, "A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture," IEEE J. Solid-State Circuits, vol.38, no.2, pp. 369-373, Feb. 2003.
13. E. B. Blecker, T. M. McDonald, O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "Digital background calibration of an algorithmic analog-todigital converter using a simplified queue," IEEE J. Solid-State Circuits, vol.38, no.6, pp. 1059-1062, Jun. 2003.
14. J. Li and U.-K. Moon, "A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique," IEEE J. Solid-State Circuits, vol.39, no.9, pp. 1468-1476, Sep. 2004.