Capacitor-Swapping Cyclic A/D Conversion Techniques With Reduced Mismatch Sensitivity

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 12, 2008, Pages 1219-1223

  Kuo, Chun Hsien ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Analog to digital converter (ADC); capacitor mis ; match; spurious free dynamic range (SFDR)

Indexed keywords

EID: 85008048317     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.2009963     Document Type: Article

References (9)

1. A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207–1215, Dec. 1993.
2. S.-Y. Chuang and T. L. Sculley, “A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 674–683, Jun. 2002.
3. J. M. Ingino and B. A. Wooley, “A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1920–1931, Dec. 1998.
4. X. Wang, P. J. Hurst, and S. H. Lewis, “A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1799–1808, Nov. 2004.
5. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, “A ratio-independent algorithmic analog-to-digital conversion technique,” IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 828–836, Dec. 1984.
6. Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139–2151, Dec. 2004.
7. P. C. Yu and H.-S. Lee, “A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854–1861, Dec. 1996.
8. P. C. Yu, S. Shehata, A. Joharapurkar, P. Chugh, A. R. Bugeja, X. Du, S.-U. Kwak, Y. Papantonopoulous, and T. Kuyel, “A 14b 40 MSample/s pipelined ADC with DFCA,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 136–137, 439–440.
9. S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954–961, Dec. 1987.