On the retention time distribution of dual-channel vertical DRAM technologies

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn 2003-January, Issue , 2003, Pages 243-246

  Beintner, J ^a   Li, Y ^b   Casarotto, D ^a   Chidambarrao, D ^b   McStay, K ^a   Wang, G ^b   Hummler, K ^a   Divakaruni, R ^b   Bergner, W ^a   Crabbe E ^b   Mueller, W ^a   Poechmueller, P ^a   Bronner, G ^b  

^a INFINEON TECHNOLOGIES   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FIELDS;

DEFECT LEVELS; DRAM TECHNOLOGY; OUT-DIFFUSION; PROBE STORAGE; RETENTION TIME; RETENTION TIME DISTRIBUTION; VERTICAL DEVICES; VERTICAL TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 78751646595     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2003.1252598     Document Type: Conference Paper

References (8)

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