A 4.3GB/s mobile memory interface with power-efficient bandwidth scaling

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 136-137

  Palmer, Robert ^a   Poulton, John ^a   Leibowitz, Brian ^a   Frans, Yohan ^a   Li, Simon ^a   Fuller, Andrew ^a   Eyles, John ^a   Wilson, John ^a   Aleksic, Marko ^a   Greer, Trey ^a   Bucher, Michael ^a   Nguyen, Nhat ^a  

^a RAMBUS INC   (United States)

Author keywords

I O; Low power; Memory; Power management

Indexed keywords

CONTROLLER INTERFACES; DATA BANDWIDTH; I/O; LOW POWER; LOW POWER STATE; MEMORY; MOBILE MEMORIES; POWER EFFICIENCY; POWER EFFICIENT; POWER MANAGEMENT; POWER STATE;

BANDWIDTH; ELECTRIC POWER MEASUREMENT; EMBEDDED SYSTEMS; ENERGY MANAGEMENT;

VLSI CIRCUITS;

EID: 70449411366     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. G. Balamurugan, et al., "A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS", IEEE JSSC, vol. 43, Apr. 2008, pp. 1010-1019.
2. K. Chang, et al., "A 16Gb/s/link, 64GB/s Bidirectional Asymmetric Memory Interface Cell," IEEE Symp. VLSI Circuits, 2008, pp. 126-127.
3. J. Poulton, et al., "A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS", IEEE JSSC, vol. 42, Dec. 2007, pp. 2745-2757.