Leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in real-time systems

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2010, Pages 357-362

  Wang, Weixun ^a   Mishra, Prabhat ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC CACHE; DYNAMIC VOLTAGE SCALING; ENERGY CONSUMPTION; ENERGY MINIMIZATION; LEAKAGE POWER; MANUFACTURING TECHNOLOGIES; MEMORY SUBSYSTEMS; POWER DISSIPATION; SYSTEM ENERGY; SYSTEM OPTIMIZATIONS; VOLTAGE-SCALING;

DESIGN; ENERGY EFFICIENCY; LEAKAGE CURRENTS; REAL TIME SYSTEMS; VOLTAGE STABILIZING CIRCUITS;

EMBEDDED SYSTEMS;

EID: 77949974202     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2010.22     Document Type: Conference Paper

References (33)

1. I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava, "Power optimization of variable-voltage core-based systems" IEEE TCAD, vol. 18, pp. 1702-1714, 1999.
2. A. Malik et al., "A low power unified cache architecture providing power and performance flexibility" ISLPED, 2000.
3. D. H. Albonesi, "Selective cache ways: On-demand cache resource allocation" Micro, 1999.
4. G. Buttazzo, Hard Real-Time Computing Systems. Kluwer, 1995.
5. J. Liu, Real-Time Systems. Prentice Hall, 2000.
6. J. A. Butts et al., "A static power model for architects" Micro, 2000.
7. S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads" ICCAD, 2002.
8. S. Borkar, "Design challenges of technology scaling" Micro, 1999.
9. N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power" Computer, vol. 36, no. 12, pp. 68-75, 2003.
10. L. Yuan, S. Leventhal, and G. Qu, "Temperature-aware leakage minimization technique for real-time systems" ICCAD, 2006.
11. H. Noori et al., "The effect of temperature on cache size tuning for low energy embedded systems" GLSVLSI, 2007.
12. R. Jejurikar, C. Pereira, and R. K. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems" DAC, 2004.
13. R. Jejurikar and R. Gupta, "Energy-aware task scheduling with task synchronization for embedded real-time systems" IEEE TCAD, vol. 25, pp. 1024-1037, 2006.
14. S. Zhang, K. Chatha, and G. Konjevod, "Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules" ISLPED, 2007.
15. S. Oh, J. Kim, S. Kim, and C. Kyung, "Task partitioning algorithm for intra-task dynamic voltage scaling" ISCAS, 2008.
16. Y.-H. Lee, K. Reddy, and C. Krishna, "Scheduling techniques for reducing leakage power in hard real-time systems" ECRTS, 2003.
17. J.-J. Chen and T.-W. Kuo, "Procrastination for leakage-aware ratemonotonic scheduling on a dynamic voltage scaling processor" LCTES, 2006.
18. J.-J. Chen and T.-W. Kuo, "Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems" ICCAD, 2007.
19. A. Gordon-Ross and F. Vahid, "A self-tuning configurable cache" DAC, 2007.
20. W. Wang, P. Mishra, and A. Gordon-Ross, "Sacr: Scheduling-aware cache reconfiguration for real-time embedded systems" in VLSI Design, 2009.
21. W. Wang and P. Mishra, "Dynamic reconfiguration of two-level caches in soft real-time embedded systems" ISVLSI, 2009.
22. C. Zhang, F. Vahid, and W. Najjar, "A highly configurable cache for low energy embedded systems" ACM TECS, vol. 6, pp. 362-387, 2005.
23. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories" ISLPED, 2000.
24. N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction" iMicro, 2002.
25. J.-W. Chi, C.-L. Yang, Y.-J. Chen, and J.-J. Chen, "Cache leakage control mechanism for hard real-time systems" CASES, 2007.
26. A. C. Nacul and T. Givargis, "Dynamic voltage and cache reconfiguration for low power" DATE, 2004.
27. H. J. M. Veendrick, "Short-circuit dissipation of static cmos circuitry and its impact on the design of buffer circuits" IEEE Journal of Solid-State Circuits, vol. 19, no. 4, pp. 468-473, Aug 1984.
28. D. Burger, T. M. Austin, and S. Bennett, "Evaluating future microprocessors: The simplescalar tool set" University of Wisconsin-Madison, Tech. Rep., 1996.
29. CACTI, CACTI, HP Labs, CACTI 4.2, http://www.hpl.hp.com/.
30. H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez, "Dynamic and aggressive scheduling techniques for power-aware real-time systems" in RTSS, 2001.
31. C. Lee, M. Potkonjak, and W. H. Mangione-smith, "Mediabench: A tool for evaluating and synthesizing multimedia and communications systems" Micro, 1997.
32. M. Guthaus, J. Ringenberg, D.Ernest, T. Austin, T. Mudge, and R. Brown, "Mibench: A free, commercially representative embedded benchmark suite" WWC, 2001.
33. EEMBC, EEMBC, The Embedded Microprocessor Benchmark Consortium, http://www.eembc.org/.