ParaLog: Enabling and accelerating online parallel monitoring of multithreaded applications

ACM SIGPLAN Notices

Volumn 45, Issue 3, 2010, Pages 271-283

  Vlachos, Evangelos ^a   Goodstein, Michelle L ^a   Kozuch, Michael A ^b   Chen, Shimin ^b   Falsafi, Babak ^c   Gibbons, Phillip B ^b   Mowry, Todd C ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c EPFL   (Switzerland)

Author keywords

Hardware support for debugging; Instruction grain lifeguards; Online parallel monitoring

Indexed keywords

COHERENCE TRAFFIC; DATA DEPENDENCE; DATAFLOW; HARDWARE DESIGN; HARDWARE SUPPORT FOR DEBUGGING; HARDWARE SUPPORTS; MULTI-THREADED APPLICATION; MULTITHREADED; OPERATING SYSTEMS; PARALLEL APPLICATION; PARALLELIZING; PARALOGS; RUNNING APPLICATIONS; SINGLE-THREADED; SYSTEM DESIGN;

COMPUTER DEBUGGING; COMPUTER OPERATING SYSTEMS; DESIGN; METADATA; MONITORING;

RISK ANALYSIS;

EID: 77949747101     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (48)

1. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In PACT, 2008.
2. D. Bruening. Efficient, Transparent, and Comprehensive Runtime Code Manipulation. PhD thesis, MIT, 2004.
3. W. R. Bush, J. D. Pincus, and D. J. Sielaff. A static analyzer for finding dynamic programming errors. Software - Practice and Experience, 30(7), 2000.
4. S. Chen, B. Falsafi, P. B. Gibbons, M. Kozuch, T. C. Mowry, R. Teodorescu, A. Ailamaki, L. Fix, G. R. Ganger, B. Lin, and S. W. Schlosser. Log-based architectures for general-purpose monitoring of deployed code. In ASID Workshop at ASPLOS, 2006.
5. S. Chen, M. Kozuch, P. B. Gibbons, M. Ryan, T. Strigkos, T. C. Mowry, O. Ruwase, E. Vlachos, B. Falsafi, and V. Ramachandran. Flexible hardware acceleration for instruction-grain lifeguards. IEEE Micro, 29(1):62-72, 2009. Top Picks from the 2008 Computer Architecture Conferences.
6. S. Chen, M. Kozuch, T. Strigkos, B. Falsafi, P. B. Gibbons, T. C. Mowry, V. Ramachandran, O. Ruwase, M. Ryan, and E. Vlachos. Flexible hardware acceleration for instruction-grain program monitoring. In ISCA, 2008.
7. J. Chung, M. Dalton, H. Kannan, and C. Kozyrakis. Thread-safe dynamic binary translation using transactional memory. In HPCA, 2008.
8. M. L. Corliss, E. C. Lewis, and A. Roth. DISE: A programmable macro engine for customizing applications. In ISCA, 2003.
9. J. R. Crandall and F. T. Chong. Minos: Control data attack prevention orthogonal to memory model. In MICRO, 2004.
10. M. Dalton, H. Kannan, and C. Kozyrakis. Raksha: A flexible information flow architecture for software security. In ISCA, 2007.
11. D. Engler, B. Chelf, A. Chou, and S. Hallem. Checking system rules using system-specific, programmer-written compiler extensions. In OSDI, 2000.
12. M. D. Ernst, J. Cockrell, W. G. Griswold, and D. Notkin. Dynamically discovering likely program invariants to support program evolution. IEEE Trans. Software Engineering, 27(2), 2001.
13. C. Flanagan, K. R. M. Leino, M. Lillibridge, G. Nelson, J. B. Saxe, and R. Stata. Extended static checking for Java. In PLDI, 2002.
14. D. Geels, G. Altekar, S. Shenker, and I. Stoica. Replay debugging for distributed applications. In USENIX ATEC, 2006.
15. C. Gniady, B. Falsafi, and T. N. Vijaykumar. Is SC + ILP = RC? In ISCA, 1999.
16. M. L. Goodstein, E. Vlachos, S. Chen, P. B. Gibbons, M. Kozuch, and T. C. Mowry. Butterfly analysis: Adapting dataflow analysis to dynamic parallel monitoring. In ASPLOS, 2010.
17. M. Herlihy and J. E. B. Moss. Transactional memory: architectural support for lock-free data structures. In HPCA, 1993.
18. D. R. Hower and M. D. Hill. Rerun: Exploiting episodes for lightweight memory race recording. In ISCA, 2008.
19. HP Labs. Cacti 5.1 Technical Report. http://www.hpl.hp.com/research/ cacti/.
20. H. Kannan. Ordering decoupled metadata accesses in multiprocessors. In MICRO, 2009.
21. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In PLDI, 2005.
22. P. Montesinos, L. Ceze, and J. Torrellas. DeLorean: Recording and deterministically replaying shared-memory multiprocessor execution efficiently. In ISCA, 2008.
23. P. Montesinos, M. Hicks, S. T. King, and J. Torrellas. Capo: A software-hardware interface for practical deterministic multiprocessor replay. In ASPLOS, 2009.
24. S. S. Mukherjee, B. Falsafi, M. D. Hill, and D. A. Wood. Coherent network interfaces for fine-grain communication. In ISCA, 1996.
25. V. Nagarajan and R. Gupta. Architectural support for shadow memory in multiprocessors. In VEE, 2009.
26. S. Narayanasamy, C. Pereira, and B. Calder. Recording shared memory dependencies using strata. In ASPLOS, 2006.
27. S. Narayanasamy, G. Pokam, and B. Calder. BugNet: Continuously recording program execution for deterministic replay debugging. In ISCA, 2005.
28. N. Nethercote. Dynamic Binary Analysis and Instrumentation. PhD thesis, U. Cambridge, 2004. http://valgrind.org.
29. N. Nethercote and J. Seward. Valgrind: A program supervision framework. Electronic Notes in Theoretical Computer Science, 89(2), 2003.
30. N. Nethercote and J. Seward. How to shadow every byte of memory used by a program. In VEE, 2007.
31. N. Nethercote and J. Seward. Valgrind: A framework for heavyweight dynamic binary instrumentation. In PLDI, 2007.
32. J. Newsome and D. Song. Dynamic taint analysis for automatic detection, analysis, and signature generation of exploits on commodity software. In NDSS, 2005.
33. E. B. Nightingale, D. Peek, P. M. Chen, and J. Flinn. Parallelizing security checks on commodity hardware. In ASPLOS, 2008.
34. G. Pokam, C. Pereira, K. Danne, R. Kassa, and A.-R. Adl-Tabatabai. Architecting a chunk-based memory race recorder in modern CMPs. In MICRO, 2009.
35. F. Qin, C.Wang, Z. Li, H. Kim, Y. Zhou, and Y. Wu. LIFT: A low-overhead practical information flow tracking system for detecting security attacks. In MICRO, 2006.
36. O. Ruwase, P. B. Gibbons, T. C. Mowry, V. Ramachandran, S. Chen, M. Kozuch, and M. Ryan. Parallelizing Dynamic Information Flow Tracking. In SPAA, 2008.
37. S. Savage, M. Burrows, G. Nelson, P. Sobalvarro, and T. Anderson. Eraser: A dynamic race detector for multi-threaded programs. ACM TOCS, 15(4), 1997.
38. R. Shetty, M. Kharbutli, Y. Solihin, and M. Prvulovic. Heapmon: A helper-thread approach to programmable, automatic, and lowoverhead memory bug detection. IBM J. on Research and Development, 50(2/3), 2006.
39. G. E. Suh, J. W. Lee, D. Zhang, and S. Devadas. Secure program execution via dynamic information flow tracking. In ASPLOS, 2004.
40. G.-R. Uh, R. Cohn, B. Yadavalli, R. Peri, and R. Ayyagari. Analyzing dynamic binary instrumentation overhead. In WBIA Workshop at ASPLOS, 2006.
41. G. Venkataramani, I. Doudalis, Y. Solihin, and M. Prvulovic. Flexi- Taint: A programmable accelerator for dynamic taint propagation. In HPCA, 2008.
42. G. Venkataramani, B. Roemer, Y. Solihin, and M. Prvulovic. Mem- Tracker: Efficient and programmable support for memory access monitoring and debugging. In HPCA, 2007.
43. Virtutech Simics. http://www.virtutech.com/.
44. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In ISCA, 1995.
45. M. Xu, R. Bodik, and M. D. Hill. A 'Flight Data Recorder' for enabling full-system multiprocessor deterministic replay. In ISCA, 2003.
46. M. Xu, R. Bodik, and M. D. Hill. A regulated transitive reduction (RTR) for longer memory race recording. In ASPLOS, 2006.
47. P. Zhou, R. Teodorescu, and Y. Zhou. HARD: Hardware-assisted lockset-based race detection. In HPCA, 2007.
48. Y. Zhou, P. Zhou, F. Qin, W. Liu, and J. Torrellas. Efficient and flexible architectural support for dynamic monitoring. ACM TACO, 2(1), 2005.