A 7.1 mW, 10 GHz all digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 3, 2010, Pages 578-586

  Yang, Song Yu ^a   Chen, Wei Zen ^b   Lu, Tai You ^b  

^a MEDIATEK INC   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

ADPLL; Bang bang phase detector; Frequency divider; Phase accumulator; Phase frequency detector; Phase locked loop

Indexed keywords

90NM CMOS; ALL DIGITAL; BANG-BANG PHASE DETECTORS; CORE AREA; DIGITAL I/O; FREQUENCY ACQUISITION; FREQUENCY DIVIDERS; HIGH-SPEED OPERATION; LOOP BANDWIDTH; LOOP FILTER; LOW NOISE; LOW-POWER DISSIPATION; PHASE ACCUMULATORS; PHASE FREQUENCY DETECTORS; PHASE TRACKING; TIMING SKEW;

CMOS INTEGRATED CIRCUITS; DETECTORS; FREQUENCY DIVIDING CIRCUITS; FREQUENCY SYNTHESIZERS; JITTER; PHASE LOCKED LOOPS; QUADRATURE AMPLITUDE MODULATION; SIGNAL DETECTION; SPURIOUS SIGNAL NOISE;

ANTENNA PHASED ARRAYS;

EID: 77649170735     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2039530     Document Type: Article

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