A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages

  Chang, Hsiang Hui ^a   Wang, Ping Ying ^a   Zhan, Jing Hong Conan ^a   Hsieh, Bing Yu ^a  

^a Media Tek ^*  (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; SPURIOUS SIGNAL NOISE;

AREA OVERHEAD; DIGITAL FILTERING; FRACTIONAL SPURS; GAIN CALIBRATION; INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE; PHASE-NOISE; REFERENCE SPUR; SYSTEM REQUIREMENTS; TIME-TO-DIGITAL CONVERTERS;

DIGITAL ARITHMETIC;

EID: 49549102895     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523126     Document Type: Conference Paper

References (3)

1. R. B. Staszewski, K. Muhammad, D. Leipold et al., "All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, Dec. 2004.
2. R. B. Staszewski, J. L. Wallberg, S. Rezeq et al., "All-Digital PLL and Transmitter for Mobile Phones," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. 2005.
3. E. Temporiti, G. Albasini, I. Bietti et al., "A 700kHz Bandwidth ΔΣ Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMAApplications," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446-1454, Sep. 2004.