Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

Microelectronics Reliability

Volumn 50, Issue 3, 2010, Pages 360-364

  Benbakhti, B ^a   Ayubi Moak, J S ^a   Kalna, K ^a   Lin, D ^b   Hellings, G ^b,c   Brammertz, G ^b   De Meyer, K ^b,c   Thayne, I ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED CHANNELS; DRIVE CURRENTS; ENERGY DISTRIBUTIONS; FLAT BAND; HIGH DENSITY; III-V MOSFET; INTERFACE STATE; PERFORMANCE CHARACTERISTICS; QUANTUM WELL; SUBTHRESHOLD; SUBTHRESHOLD CHARACTERISTICS; SURFACE CHANNEL; SURFACE CHANNEL DEVICES; TCAD SIMULATION; TRAP DENSITY;

ELECTRON MOBILITY; HIGH ELECTRON MOBILITY TRANSISTORS; MOSFET DEVICES; SEMICONDUCTOR QUANTUM WELLS;

CURRENT VOLTAGE CHARACTERISTICS;

EID: 76849096843     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.11.017     Document Type: Article

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