Effect of interface state trap density on the characteristics of n-type, enhancement-mode, implant-free In0.3Ga0.7As MOSFETs

Microelectronic Engineering

Volumn 86, Issue 7-9, 2009, Pages 1564-1567

  Ayubi Moak, J ^a   Benbakhti, B ^a   Kalna, K ^a   Paterson, G W ^a   Hill, R ^a   Passlack, M ^b   Thayne, I ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Drift diffusion; III V MOSFETs; Interface state trap density

Indexed keywords

DEVICE CHARACTERISTICS; DEVICE SIMULATIONS; DRIFT-DIFFUSION; ENHANCEMENT-MODE; GATE LENGTH; III-V MOSFETS; INTERFACE STATE; INTERFACE STATE TRAP DENSITY; MOS-FET; MOSFETS; SUBTHRESHOLD CHARACTERISTICS; TRAP DENSITY;

DIFFUSION; GALLIUM;

MOSFET DEVICES;

EID: 67349090036     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.03.024     Document Type: Article

References (7)

1. M. Passlack, O. Hartin, M. Ray, N. Medendorp, US Patent 6 963 090, 2005.
2. Passlack M., Rajagopalan K., Abrokwah J., and Droopad R. IEEE Trans. Electron Devices 53 (2006) 2454
3. Hill R.J.W., Moran D.A.J., Li X., Zhou H., Macintyre D., Thoms S., Asenov A., Zurcher P., Rajagopalan K., Abrokwah J., Droopad R., Passlack M., and Thayne I.G. Electron Device Lett. 28 (2007) 1080
4. Passlack M. Material Fundamentals of Gate Dielectrics (2005), Springer, Dordrecht, The Netherlands
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