An H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Fujiyoshi, Toshihide ^a   Shiratake, Shinichiro ^a   Nomura, Shuou ^a   Nishikawa, Tsuyoshi ^a   Kitasho, Yoshiyuki ^a   Arakida, Hideho ^a   Okuda, Yuji ^a   Tsuboi, Yoshiro ^a   Hamada, Mototsugu ^a   Hara, Hiroyuki ^a   Fujita, Tetsuya ^a   Hatori, Fumitoshi ^a   Shimazawa, Takayoshi ^a   Yahagi, Kunihiko ^a   Takeda, Hideki ^a   Murakata, Masami ^a   Minami, Fumihiro ^a   Kawabe, Naoyuki ^a   Kitahara, Takeshi ^a   Seta, Katsuhiro ^a   Takahashi, Masafumi ^a   Oowaki, Yukihito ^a   more..

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144440672     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Tanabe et al., "Visconti: Multi-VLIW Image Recognition Processor based on Configurable Processor," IEEE Custom-Integrated Circuits Conference, pp. 185-188, 2003.
2. T. Nishikawa et al., "A 60MHz 240mW MPEG-4 Video-Phone LSI with 16Mb Embedded DRAM," ISSCC Dig. Tech. Papers, pp. 230-231, Feb., 2000.
3. H. Arakida et al., "A 125MHz 160mW, 80nA Standby, MPEG-4 Audiovisual LSI with 16Mb Embedded DRAM and a 5GOPS Adaptive Post Filter," ISSCC Dig. Tech. Papers, pp.42-43, Feb., 2003.
4. S. Akui et al., "Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor," ISSCC Dig. Tech. Papers, pp. 64-65, Feb., 2004.
5. T. Saeki et al., "A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay," ISSCC Dig. Tech. Papers, pp. 374-375, Feb., 1996.