Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 467-470

  Hirano, Y ^a   Matsumoto, T ^a   Maeda, S ^a   Iwamatsu, T ^a   Kunikiyo, T ^a   Nii, K ^a   Yamamoto, K ^a   Yamaguchi, Y ^a   Ipposhi, T ^a   Maegawa, S ^a   Inuishi, M ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; ERROR CORRECTION; GATES (TRANSISTOR); HYBRID INTEGRATED CIRCUITS; LSI CIRCUITS; STATIC RANDOM ACCESS STORAGE;

HYBRID-TRENCH-ISOLATION (HTI) TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 17344383097     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)