Low power current-mode binary-tree asynchronous Min/Max circuit

Microelectronics Journal

Volumn 41, Issue 1, 2010, Pages 64-73

  DŁugosz, RafaŁ ^a   Talaśka, Tomasz ^b  

^a EPFL   (Switzerland)

^b UNIVERSITY OF TECHNOLOGY AND LIFE SCIENCES   (Poland)

Author keywords

Asynchronous circuits; Current mode; Kohonen neural networks; Min Max circuits; Nonlinear filters; Parallel data processing

Indexed keywords

ASYNCHRONOUS CIRCUITS; CURRENT MODE; KOHONEN NEURAL NETWORKS; NONLINEAR FILTER; PARALLEL DATA PROCESSING;

DATA PROCESSING; NETWORKS (CIRCUITS); NONLINEAR FILTERING;

NEURAL NETWORKS;

EID: 75149167081     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2009.12.009     Document Type: Article

References (33)

1. Kohonen T. Self-organizing Maps (2001), Springer Verlag, Berlin
2. Choi J., and Sheu B.J. A high-precision VLSI winner-take-all circuit for self-organizing neural networks. IEEE Journal of Solid-State Circuits 28 5 (1993) 576-584
3. L.J. Van Vliet, Robust local max-min filters by normalized power-weighted filtering, in: International Conference on Pattern Recognition (ICPR), 2004, pp. 696-699.
4. Vemis M., Economou G., Fotopoulos S., and Khodyrev A. The use of Boolean functions and logical operations for edge detection in images. Signal Processing 45 2 (1995) 161-172
5. Jackway P.T., and Deriche M. Scale-space properties of the multiscale morphological dilation-erosion. IEEE Transactions on Pattern Analysis and Machine Intelligence 18 1 (1996) 38-51
6. K. Wawryn, B. Strzeszewski, Current mode AB class WTA circuit, in: The IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2001, pp. 293-296.
7. Starzyk J.A., and Fang X. CMOS current-mode winner-take-all circuit with both excitatory and inhibitory feedback. Electronics Letters 29 10 (1993) 908-910
8. Serrano T., and Linares-Barranco B. A modular current-mode high-precision winner-take-all circuit. IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing 42 2 (1995) 132-134
9. Moses W.W., Beuville E., and Ho M.H. A winner-take-all IC for determining the crystal of interaction in PET detectors. IEEE Transactions on Nuclear Science 43 3 (1996) 1615-1618
10. G.T. Tuttle, S. Fallahi, A.A. Abidi, An 8-b CMOS vector A/D converter, in: IEEE International Solid-State Circuit Conference (ISSCC), San Francisco, USA, 1993, pp. 38-39.
11. Serrano-Gotarredona T., and Linares Barranco B. A high-precision current mode WTA-MAX circuit with multichip capability. IEEE Journal of Solid-State Circuits 33 2 (1998) 280-286
12. Demosthenous A., Smedley S., and Taylor J. A CMOS analog winner-takes-all network for large-scale applications. IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications 45 3 (1998) 300-304
13. Ramirez-Angulo J., Molinar-Solis J.E., Gupta S., Carvajal R.G., and Lopez-Martin A.J. A high-swing, high-speed CMOS WTA using differential flipped voltage followers. IEEE Transactions on Circuits and Systems II: Express Briefs 54 8 (2007) 668-672
14. Lazzaro J., Ryckebusch S., Mahowald M.A., and Mead C.A. Winner-take-all of O(n) complexity. In: Touretzky D.S. (Ed). Advances in Neural Signal Processing Systems (1989), Morgan Kaufmann Publishers, Inc., San Francisco 703-711
15. B. Tomatsopoulos, A. Demosthenous, Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits, in: European Conference on Circuit Theory and Design (ECCTD), 3 (28), Cork, Ireland, 2005, pp. 241-244.
16. B.M. Wilamowski, D.L. Jordan, O. Kaynak, Low power current mode loser-take-all circuit for image compression, in: NASA Symposium on VLSI Design, 2000, pp. 7.6.1-7.6.8.
17. Fish A., Milrud V., and Yadid-Pecht O. High-speed and high-precision current winner-take-all circuit. IEEE Transactions on Circuits and Systems II: Express Briefs 52 3 (2005) 131-135
18. L.A. Sanchez-Gaspariano, A. Dlaz-Sanchez, G. Saldana-Gonzalez, High-precision current-based CMOS WTA/LTA filters, in: Proceedings of the International Conference on Electronics, Communications and Computers (CONIELECOMP), 2007, pp. 25-31.
19. Y.C. Hung, B.D. Liu, High-reliability programmable WTA/LTA circuit of O(N) complexity using a single comparator, in: IEE Proceedings-Circuits Devices and Systems, 151 (6), 2004, pp. 579-586.
20. Yu Chien-Cheng, Tang Yun-Ching, Liu Bin-Da, Design of high performance CMOS current-mode winner-take-all circuit, in: Proceedings of the International Conference on ASIC, Beijing, China, 2003, pp. 568-572.
21. Yu Gwo-Jeng, Liu Bin-Da, Huang Chun-Yueh, Bi-directional current-mode multiple input maximum circuit, in: Asia Pacific Conference on ASICs (AP-ASIC), Cheju, South Korea, 2000, pp. 41-44.
22. R. DŁugosz, T. Talaśka, R. Wojtyna., New binary-tree-based winner-takes-all circuit for learning on silicon Kohonen's networks, in: Int. Conf. on Signals and Electronic Systems (ICSES), łódź, Poland, 2006, pp. 441-446.
23. Talaśka T., and DŁugosz R. Current mode Euclidean distance calculation circuit for Kohonen's neural network implemented in CMOS 0.18 μm technology. Canadian Conference on Electrical and Computer Engineering (CCECE) (2007), Vancouver, Canada 437-440
24. Talaśka T., DŁugosz R., and Pedrycz W. Adaptive weight change mechanism for Kohonen neural network implemented in CMOS 0.18 μm Technology. European Symposium on Artificial Neural Networks (ESANN) (2007), Bruges, Belgium 151-156
25. Talaśka T., and DŁugosz R. Initialization mechanism in Kohonen neural network implemented in CMOS technology. European Symposium on Artificial Neural Networks (ESANN) (2008), Bruges, Belgium 337-342
26. Chen Shih-Lun, Lee Ho-Yin, Chu Yu-Wen, Chen Chiung-An, Lin Chin-Chun, Luo Ching-Hsing, A variable control system for wireless body sensor network, in: IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 2034-2037.
27. Wei Zhang, Shenqi Jing, Lin Gui, Yongkui Zhang, Physiological data acquisition system for education assessment using wireless sensor network, in: International Conference on Technology and Applications in Biomedicine (ITAB), Shenzhen, China, 2008, pp. 471-473.
28. T. Talaśka, R. DŁugosz, J. Dalecki, W. Pedrycz, R. Wojtyna, Experimental results of CMOS-implemented conscience mechanism applied for WTA networks, in: Proceedings of the International Conference on Signals and Electronic Systems (ICSES), Krakow, Poland, 2008, pp. 101-104.
29. Croon J.A., Rosmeulen M., Decoutere S., Sansen W., and Maes H.E. An easy-to-use mismatch model for the MOS transistor. IEEE Journal of Solid-State Circuits 37 8 (2002) 1056-1064
30. R. Difrenza, P. Llinares, G. Morin, E. Granger, G. Ghibaudo, A new model for threshold voltage mismatch based on the random fluctuations of dopant number in the MOS transistor gate, in: European Solid-State Device Research Conference, 2001, pp. 299-302.
31. M. Conti, G.F.D. Betta, S. Orcioni, G. Soncini, C. Turchetti, N. Zorzi, Test structure for mismatch characterization of MOS transistors in subthreshold regime, in: IEEE International Conference on Microelectronic Test Structures (ICMTS), vol. 10, 1997, pp. 173-178.
32. Difrenza R., Llinares P., and Ghibaudo G. A new model for the current factor mismatch in the MOS transistor. Solid-State Electronics 47 7 (2003) 1167-1171
33. R. DŁugosz, K. Iniewski, Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks, VLSI Design Journal, Hindavi Publishing, vol. 2007, Article ID 45269.