메뉴 건너뛰기




Volumn 151, Issue 6, 2004, Pages 579-586

High-reliability programmable CMOS WTA/LTA circuit of O(N) complexity using a single comparator

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; COMPUTER SIMULATION; LOGIC GATES; MONTE CARLO METHODS; SCHEMATIC DIAGRAMS; THRESHOLD VOLTAGE; TRANSISTORS; VLSI CIRCUITS;

EID: 13244251084     PISSN: 13502409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cds:20040654     Document Type: Article
Times cited : (10)

References (21)
  • 1
    • 0023331258 scopus 로고
    • 'An introduction to computing with neural nets'
    • Lippmann, R.: 'An introduction to computing with neural nets', IEEE ASSP Mag., 1987, 4, (2), pp. 4-22
    • (1987) IEEE ASSP Mag. , vol.4 , Issue.2 , pp. 4-22
    • Lippmann, R.1
  • 3
    • 0027597003 scopus 로고
    • 'CMOS current mode winner-take-all circuit with both excitatory and inhibitory feedback'
    • Starzyk, J.A., and Fang, X.: 'CMOS current mode winner-take-all circuit with both excitatory and inhibitory feedback', Electron. Lett., 1993, 29, (10), pp. 908-910
    • (1993) Electron. Lett. , vol.29 , Issue.10 , pp. 908-910
    • Starzyk, J.A.1    Fang, X.2
  • 5
    • 0000124172 scopus 로고
    • 'A scalable high-speed current-mode winner-take-all network for VLSI neural applications'
    • Smedley, S., Taylor, J., and Wilby, M.: 'A scalable high-speed current-mode winner-take-all network for VLSI neural applications', IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 1995, 42, (5), pp. 289-291
    • (1995) IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. , vol.42 , Issue.5 , pp. 289-291
    • Smedley, S.1    Taylor, J.2    Wilby, M.3
  • 6
    • 0031996752 scopus 로고    scopus 로고
    • 'A high-precision current-mode wta-max circuit with multichip capability'
    • Gotarredona, T.S., and Barranco, B.L.: 'A high-precision current-mode wta-max circuit with multichip capability', IEEE J. Solid-State Circuits, 1998, 33, (2), pp. 280-286
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.2 , pp. 280-286
    • Gotarredona, T.S.1    Barranco, B.L.2
  • 8
    • 33646211171 scopus 로고    scopus 로고
    • 'A high-precision self-adaptive analog CMOS current-mode maximum/minimum circuit with O(N) complexity for rank-order extractor'
    • Proc. Int. Analog VLSI Workshop, Bangkok, Thailand, May 2001
    • Hung, Y.C., and Liu, B.D.: 'A high-precision self-adaptive analog CMOS current-mode maximum/minimum circuit with O(N) complexity for rank-order extractor'. Proc. 2001 Int. Analog VLSI Workshop, Bangkok, Thailand, May 2001, pp. 1-6
    • (2001) , pp. 1-6
    • Hung, Y.C.1    Liu, B.D.2
  • 9
    • 33646209321 scopus 로고    scopus 로고
    • 'A self-feedback high-speed CMOS loser-takes-all circuit for vector-quantizer application'
    • Proc. Int. Symp. on Communications, Tainan, Taiwan, Nov. 2001
    • Hung, Y.C., and Liu, B.D.: 'A self-feedback high-speed CMOS loser-takes-all circuit for vector-quantizer application'. Proc. 2001 Int. Symp. on Communications, Tainan, Taiwan, Nov. 2001, pp. 16.5.1-16.5.4
    • (2001)
    • Hung, Y.C.1    Liu, B.D.2
  • 10
    • 0036754226 scopus 로고    scopus 로고
    • 'A 1.2-V rail-to-rail analog CMOS rank-order filter with k-WTA capability'
    • Hung, Y.C., and Liu, B.D.: 'A 1.2-V rail-to-rail analog CMOS rank-order filter with k-WTA capability', Analog Integr. Circuits Signal Process., 2002, 32, (3), pp. 219-230
    • (2002) Analog Integr. Circuits Signal Process. , vol.32 , Issue.3 , pp. 219-230
    • Hung, Y.C.1    Liu, B.D.2
  • 11
    • 0027912063 scopus 로고
    • 'Min-net winner-take-all CMOS implementation'
    • He, Y., and Sanchez-Sinencio, E.: 'Min-net winner-take-all CMOS implementation', Electron. Lett., 1993, 29, (14), pp. 1237-1239
    • (1993) Electron. Lett. , vol.29 , Issue.14 , pp. 1237-1239
    • He, Y.1    Sanchez-Sinencio, E.2
  • 12
    • 0027590834 scopus 로고
    • 'A high-precision VLSI winner-take-all circuit for self-organizing neural networks'
    • Choi, J., and Sheu, B.J.: 'A high-precision VLSI winner-take-all circuit for self-organizing neural networks', IEEE J. Solid-State Circuits 1993, 28, (5), pp. 576-583
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.5 , pp. 576-583
    • Choi, J.1    Sheu, B.J.2
  • 13
    • 0030172843 scopus 로고    scopus 로고
    • 'A winner-take-all IC for determining the crystal of interaction in PET detectors'
    • Moses, W.W., Beuville, E., and Ho, M.H.: 'A winner-take-all IC for determining the crystal of interaction in PET detectors', IEEE Trans. Nucl. Sci., 1996, 43, (3), pp. 1615-1618
    • (1996) IEEE Trans. Nucl. Sci. , vol.43 , Issue.3 , pp. 1615-1618
    • Moses, W.W.1    Beuville, E.2    Ho, M.H.3
  • 15
    • 0036098686 scopus 로고    scopus 로고
    • 'A high-precision high-resolution WTA-MAX circuit of O(N) complexity'
    • Aksin, D. Y.: 'A high-precision high-resolution WTA-MAX circuit of O N) complexity', IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 2002, 49, (1), pp. 48-53
    • (2002) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , vol.49 , Issue.1 , pp. 48-53
    • Aksin, D.Y.1
  • 16
    • 0025382945 scopus 로고
    • 'An 8-bit 20-MS/ s CMOS A/D converter with 50-mW power consumption'
    • Hosotani, S., Miki, T., Maeda, A., and Yazawa, N.: 'An 8-bit 20-MS/ s CMOS A/D converter with 50-mW power consumption', IEEE J. Solid-State Circuits, 1990, 25, (1), pp. 167-172
    • (1990) IEEE J. Solid-State Circuits , vol.25 , Issue.1 , pp. 167-172
    • Hosotani, S.1    Miki, T.2    Maeda, A.3    Yazawa, N.4
  • 17
    • 0024611252 scopus 로고
    • 'High-speed CMOS circuit technique'
    • Yuan, J., and Stensson, C.: 'High-speed CMOS circuit technique', IEEE J. Solid-State Circuits, 1989, 24, (1), pp. 62-69
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.1 , pp. 62-69
    • Yuan, J.1    Stensson, C.2
  • 18
    • 0021477881 scopus 로고
    • 'Switch-induced error voltage on a switched capacitor'
    • Sheu, B., and Hu, C.: 'Switch-induced error voltage on a switched capacitor', IEEE J. Solid-State Circuits, 1984, 19, (4), pp. 519-525
    • (1984) IEEE J. Solid-State Circuits , vol.19 , Issue.4 , pp. 519-525
    • Sheu, B.1    Hu, C.2
  • 20
    • 80155141422 scopus 로고    scopus 로고
    • 'A CMOS vector quantizer for pattern recognition'
    • Seoul, South Korea, Aug
    • Hung, Y.C., and Liu, B.D.: 'A CMOS vector quantizer for pattern recognition'. Proc. IEEE 1st AP-ASIC, Seoul, South Korea, Aug. 1999, pp. 112-115
    • (1999) Proc. IEEE 1st AP-ASIC , pp. 112-115
    • Hung, Y.C.1    Liu, B.D.2
  • 21
    • 33646216209 scopus 로고    scopus 로고
    • 'Low-voltage low-power CMOS similarity measurement chip for binary pattern identification'
    • Hualien, Taiwan, Aug
    • Hung, Y.C., Tsai, C.Y., and Liu, B.D.: 'Low-voltage low-power CMOS similarity measurement chip for binary pattern identification'. Proc. 14th VLSI Design/CAD Symp., Hualien, Taiwan, Aug. 2003, pp. 333-336
    • (2003) Proc. 14th VLSI Design/CAD Symp. , pp. 333-336
    • Hung, Y.C.1    Tsai, C.Y.2    Liu, B.D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.