New binary-tree-based winner-takes-all circuit for learning on silicon kohonen's networks

ICSES'06 - International Conference on Signals and Electronic Systems, Proceedings

Volumn , Issue , 2006, Pages 441-444

  Długosz, Rafał ^a,b   Talaśka, Tomasz ^c   Wojtyna, Ryszard ^c  

^a POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

^b UNIVERSITY OF ALBERTA   (Canada)

^c UNIVERSITY OF TECHNOLOGY AND LIFE SCIENCES   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS ENGINEERING; FIGHTER AIRCRAFT;

CURRENT DETECTION; CURRENT MODE (CM); KOHONEN; LOW POWER (LP) APPLICATIONS; POWER CONDITIONING; SIMULATION RESULTS; SUPPLY VOLTAGES;

NEURAL NETWORKS;

EID: 58449132245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. K. Wawryn, B. Strzeszewski, "Current mode AB class WTA circuit", Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on Volume 1, pp.293 - 296, 2001.
2. K. Wawryn, B. Strzeszewski, "Prototype low power WTA circuits for programmable neural networks", IEEE International Symposium on Circuits and Systems, ISCAS 2000, Geneva, Switzerland, vol. 5, pp. 753- 756, 2000.
3. A. Demosthenous, S. Smedley, J. Taylor, "A CMOS analog Winner-Takes-All network for large-scale applications", IEEE Transactions on circuits and systems-I: Fundamental theory and Applications, Vol. 45, No. 3, 1998.
4. T. Kohonen, "Self-organizing maps", 3-ed, Springer Verlag, Berlin Heidelberg ,2001.
5. A. S. Sedra, C. W. Roberts, and F. Gohh, "The current-conveyors: History, progress and new results," Proc. Inst. Elect. Eng., pt. G, vol. 137, no. 2, Apr. 1990.
6. T. Talaśka., R. Wojtyna, "Process of winning neuron detection implemented in CMOS 0.18 μm", 5-th National Conference on Electronics KKE2006, Darłówko Wschodnie, Poland, June 2006 (In Polish).
7. T. Talaśka, R. Wojtyna., R. Długosz, K. Iniewski, "Implementation of the conscience mechanism for Kohonen's neural network in CMOS 0.18μm technology", International Conference Mixed Design of Integrated Circuits and Systems, Gdynia, Poland, June 2006.
8. R. Wojtyna, "Simple CMOS transconductance-mode differential squarer", IEEE Workshop Signal Processing '2005, Poznań, Poland, pp. 171-177, September 2005.
9. M. Sasaki, T. Inoue, Y. Shirai, F. Ueno, "Fuzzy multiple-input maximum and minimum circuits in current mode and their analyzes using bounded-difference equations", IEEE Trans. Comput., vol. 39, pp. 768-774, June 1990.
10. G. T. Turtle, S. Fallahi, A. Abidi, "An 8-b CMOS vector A/D converter", In Proc. IEEE Int. Solid-State Conf. (ISSCC), pp. 38-39, San Francisco, CA, Feb. 1993.
11. Y.-C. Hung, B.-D. Liu, "High-reliability programmable WTA/LTA circuit of O/N complexity using a single comparator", IEE Proc.-Circuits Devices Syst., Vol.151, No. 6, December 2004