Test structure for mismatch characterization of MOS transistors in subthreshold regime

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1997, Pages 173-178

  Conti, Massimo ^a   Betta, GianFranco Dalla ^a   Orcioni, Simone ^a   Soncini, Giovanni ^a   Turchetti, Claudio ^a   Zorzi, Nicola ^a  

^a UNIVERSITÀ POLITECNICA DELLE MARCHE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; PARAMETER ESTIMATION; REGRESSION ANALYSIS;

MULTIPLE LINEAR REGRESSION;

MOSFET DEVICES;

EID: 0030711964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M.J.M. Pelgrom, A.CJ. Duinmaijeq A.P.G. Welbers, "Matching properties of MOS transistors", EEiE Jou. of Solid-state Circuits, Vol. 24, n.5,p.1433-1439, Oct. 1989.
2. A. Pavasovic, A.G. Andreou, C.R. Westgate, "Charactaimtion of subthreshold MOS mismatch in transistors for VLSI systems", Jou. of VLSI Signal Processing, 8, p.75-85, 1994.
3. M. Conti, S. Orcioni, C. Turchetti, "A class of neural networks based on approximate identity for analog IC's hardware implementation", IEICE Trans. on Fundamentals of Electronics Communications and Computer Science, Japan, Vol.E77-A, n.6, pp. 1069-1079, June 1994.
4. Y. Bard, "Nonlinear parameter estimation", Academic Press, 1974.