Current mode AB class WTA circuit

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2001, Pages 293-296

  Wawryn, Krzysztof ^a   Strzeszewski, Bogdan ^a  

^a KOSZALIN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT MODE; LOW POWER; OTHER APPLICATIONS;

NETWORKS (CIRCUITS); NEURAL NETWORKS;

VLSI CIRCUITS;

EID: 36249019803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y. He, E. Sanchez-Sinencio, Min-net winner-takeall CMOS implementation, Electron. Lett., July 1993, Vol. 29, pp. 1237-1239.
2. J. Choi, B. Sheu, A high-precision VLSI winner take- all circuit for self-organising neural networks, IEEE J. Solid-state circuits, May 1993, Vol. 28, pp. 576-584.
3. S. Smedley, J. Taylor, M. Wilby, A scalable high speed current-mode winner-take-all network for VLSI neural applications, IEEE Trans. Circuits Syst., May 1995, Part I, Vol. 42, pp. 289-291.
4. A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, J. Taylor, Enhanced modular CMOS current-mode winner-take-all network, in Proc. ICECS, Rodos, 1996, Vol. 1, pp. 402-405.
5. K. Wawryn, B. Strzeszewski, Low power VLSI neuron cells for artificial neural networks, in Proc. ISCAS, Atlanta, 1996, Vol. 3, pp. 372-375.
6. K. Wawryn, B. Strzeszewski, "Prototype low power WTA circuits for programmable neural networks", in Proc. ISCAS, Geneva, Switzerland, 2000, Vol. 5, pp. 753-756.