Pipelining-based high throughput low energy mapping on network-on-chip

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 427-432

  Yu, Ming Yan ^a   Li, Ming ^a   Song, Jun Jie ^a   Fu, Fang Fa ^a   Bai, Yu Xin ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

Mapping; Network on chip; Pipeline; Scheduling

Indexed keywords

COMMUNICATION SCHEDULING; CYCLE-ACCURATE SIMULATORS; DESIGN APPROACHES; ENERGY AWARE; ENERGY CONSUMPTION; HIGH THROUGHPUT; LOW ENERGIES; MAPPING ALGORITHMS; NETWORK ON CHIP; NOC ARCHITECTURES; PIPELINED IMPLEMENTATION; STREAMING APPLICATIONS; SYSTEMC; TASK ALLOCATION;

CONFORMAL MAPPING; ELECTRIC LOAD FORECASTING; ELECTRIC NETWORK TOPOLOGY; MULTIMEDIA SIGNAL PROCESSING; PIPELINES; SIGNAL PROCESSING;

THROUGHPUT;

EID: 74549217888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.138     Document Type: Conference Paper

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