Application mapping for chip multiprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 620-625

  Chen, Guangyu ^a   Li, Feihui ^b   Son, S W ^c   Kandemir, M ^c  

^a MICROSOFT   (United States)

^b NVIDIA   (United States)

^c PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Application mapping; Chip multiprocessing; Compilers; NoC (Network on Chip); Power optimization

Indexed keywords

APPLICATIONS; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; INDUSTRIAL ENGINEERING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; SYSTEMS ANALYSIS;

APPLICATION MAPPING; CHIP MULTIPROCESSING; COMPILERS; NOC (NETWORK ON CHIP); POWER OPTIMIZATION;

PROGRAM COMPILERS;

EID: 51549094430     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555892     Document Type: Conference Paper

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