-
1
-
-
44049096221
-
-
Arteris. A comparison of network-on-chip and busses, 2005.
-
Arteris. A comparison of network-on-chip and busses, 2005.
-
-
-
-
2
-
-
34548126965
-
On design and analysis of a feasible network-on-chip (noc) architecture
-
IEEE Computer Society
-
J. H. Bahn et al. On design and analysis of a feasible network-on-chip (noc) architecture. In Proc. of ITNG, pages 1033-1038. IEEE Computer Society, 2007.
-
(2007)
Proc. of ITNG
, pp. 1033-1038
-
-
Bahn, J.H.1
-
3
-
-
0036149420
-
Networks on chips: A new soc paradigm
-
L. Benini et al. Networks on chips: A new soc paradigm. Computer, 35(1):70-78, 2002.
-
(2002)
Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
-
4
-
-
33745800231
-
A survey of research and practices of network-on-chip
-
T. Bjerregaard et al. A survey of research and practices of network-on-chip. ACM Comput. Surv., 38(1):1, 2006.
-
(2006)
ACM Comput. Surv
, vol.38
, Issue.1
, pp. 1
-
-
Bjerregaard, T.1
-
5
-
-
0034848112
-
Route packets, not wires: On-chip inteconnection networks
-
ACM Press
-
W. J. Dally et al. Route packets, not wires: on-chip inteconnection networks. In Proc. of DAC, pages 684-689. ACM Press, 2001.
-
(2001)
Proc. of DAC
, pp. 684-689
-
-
Dally, W.J.1
-
6
-
-
0028513557
-
The turn model for adaptive routing
-
C. J. Glass et al. The turn model for adaptive routing. J. ACM, 41(5):874-902, 1994.
-
(1994)
J. ACM
, vol.41
, Issue.5
, pp. 874-902
-
-
Glass, C.J.1
-
7
-
-
27344456043
-
-
K. Goossens et al. Æthereal network on chip: Concepts, architectures, and implementations. IEEE Des. Test, 22(5):414-421, 2005.
-
K. Goossens et al. Æthereal network on chip: Concepts, architectures, and implementations. IEEE Des. Test, 22(5):414-421, 2005.
-
-
-
-
8
-
-
22944476657
-
Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
-
IEEE Computer Society
-
J. Hu et al. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In Proc. of DATE, page 10234. IEEE Computer Society, 2004.
-
(2004)
Proc. of DATE
, pp. 10234
-
-
Hu, J.1
-
9
-
-
33646903750
-
A generic rtos model for real-time systems simulation with systemc
-
IEEE Computer Society
-
R. L. Moigne et al. A generic rtos model for real-time systems simulation with systemc. In Proc. of DATE, page 30082. IEEE Computer Society, 2004.
-
(2004)
Proc. of DATE
, pp. 30082
-
-
Moigne, R.L.1
-
10
-
-
27644494723
-
Key research problems in noc design: A holistic perspective
-
U. Y. Ogras et al. Key research problems in noc design: a holistic perspective. In Proc. of CODES+ISSS, pages 69-74, 2005.
-
(2005)
Proc. of CODES+ISSS
, pp. 69-74
-
-
Ogras, U.Y.1
-
11
-
-
11844249902
-
An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration
-
A. Radulescu et al. An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on CAD of Integrated Circuits and Systems, 24(1):4-17, 2005.
-
(2005)
IEEE Trans. on CAD of Integrated Circuits and Systems
, vol.24
, Issue.1
, pp. 4-17
-
-
Radulescu, A.1
-
12
-
-
27544463701
-
Near-optimal worst-case throughput routing for two-dimensional mesh networks
-
IEEE Computer Society
-
D. Seo et al. Near-optimal worst-case throughput routing for two-dimensional mesh networks. In Proc. of ISCA, pages 432-443. IEEE Computer Society, 2005.
-
(2005)
Proc. of ISCA
, pp. 432-443
-
-
Seo, D.1
-
14
-
-
34548858682
-
An 80-tile 1.28tflops network-on-chip in 65nm cmos
-
Digest of Technical Papers, IEEE International
-
S. Vangal et al. An 80-tile 1.28tflops network-on-chip in 65nm cmos. In ISSCC Digest of Technical Papers., pages 98,589. IEEE International, 2007.
-
(2007)
ISSCC
, pp. 98-589
-
-
Vangal, S.1
|