Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits

2009 International Symposium on System-on-Chip - Proceedings, SoC 2009

Volumn , Issue , 2009, Pages 118-123

  Milojevic, A Dragomir ^a,b   Radojcic, B Riko ^a,b   Carpentet, C Roger ^c,d   Marchal, D Pol ^c,d  

^a UNIVERSITÉ LIBRE DE BRUXELLES   (Belgium)

^b QUALCOMM INC   (United States)

^c Javelin DA   (United States)

^d IMEC   (Belgium)

Author keywords

3D stacked integrated circuits; High level synthesis; Virtual prototyping

Indexed keywords

3-D INTEGRATION; 3D DESIGN; DESIGN METHODOLOGY; DESIGN SPACE EXPLORATION; DRAM MEMORIES; EDA TOOLS; HIGH FIDELITY; HIGH LEVEL SYNTHESIS; NEW DESIGN; OFF-CHIP; OPTIMISATIONS; PATHFINDING; PHYSICAL DESIGN; SYSTEM LEVEL DESIGN; TECHNOLOGY NODES; TECHNOLOGY OPTIONS; TYPICAL DESIGN; VIDEO CODING; VIRTUAL PROTOTYPING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHIP SCALE PACKAGES; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; SPACE RESEARCH; THREE DIMENSIONAL; VISUAL COMMUNICATION;

DESIGN;

EID: 74549114891     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2009.5335663     Document Type: Conference Paper

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