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Volumn , Issue , 2008, Pages 125-130

Virtual design for technology exploration - A process design integration methodology for a fabless entity

Author keywords

Design methodology; Prediction methods; System analysis and design; Technology assessment; Technology forecasting

Indexed keywords

COMPETITION; ELECTRONICS INDUSTRY; INDUSTRIAL ECONOMICS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; PROCESS DESIGN; TECHNOLOGY;

EID: 50849085976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567261     Document Type: Conference Paper
Times cited : (4)

References (13)
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    • th European Solid State Device Research Conference, Montreox, Switzerland, Sep 2006
  • 2
    • 51849113983 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors, Dec
    • International Technology Roadmap for Semiconductors, 2007, Dec 2007
    • (2007) , vol.2007
  • 3
    • 81255187613 scopus 로고    scopus 로고
    • Integrated Fabless Manufacturing - the technical and business model for the future
    • Mike Campbell, "Integrated Fabless Manufacturing - the technical and business model for the future", IEEE SW Test Workshop, 2006
    • (2006) IEEE SW Test Workshop
    • Campbell, M.1
  • 4
    • 0003776777 scopus 로고    scopus 로고
    • An Introduction to System Level Modeling in SystemC 2.0
    • a white paper for Open SystemC Initiative OSCI
    • Stuart Swan, "An Introduction to System Level Modeling in SystemC 2.0", a white paper for Open SystemC Initiative (OSCI), 2001
    • (2001)
    • Swan, S.1
  • 5
    • 33750600861 scopus 로고    scopus 로고
    • New generation of predictive technology model for sub-45nm early design exploration
    • November
    • W. Zhao, Y. Cao, "New generation of predictive technology model for sub-45nm early design exploration," IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006..
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.11 , pp. 2816-2823
    • Zhao, W.1    Cao, Y.2
  • 6
    • 51849130143 scopus 로고    scopus 로고
    • Virtual prototype revived
    • July 10
    • Richard Goering, "Virtual prototype revived", EE Times, July 10,2006
    • (2006) EE Times
    • Goering, R.1
  • 8
    • 51849168814 scopus 로고    scopus 로고
    • Phillip Christie, System-level performance analysis of advanced CMOS, ESSCIRC-ESSDERC, Grenoble, France, Sep 2005
    • Phillip Christie, "System-level performance analysis of advanced CMOS", ESSCIRC-ESSDERC, Grenoble, France, Sep 2005
  • 12
    • 84938578084 scopus 로고    scopus 로고
    • Papanicolaou, Antoni s Miranda, Miguel Marchai, Pol Dierickx, Bart Catthoor, Francky, At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted, IEEE Custom Integrated Circuits Conference, Sept, 2007.
    • Papanicolaou, Antoni s Miranda, Miguel Marchai, Pol Dierickx, Bart Catthoor, Francky, "At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted", IEEE Custom Integrated Circuits Conference, Sept, 2007.
  • 13
    • 51849122657 scopus 로고    scopus 로고
    • Miguel Miranda, Variability Aware Timing/Energy Modeling of SoCs, tutorial at Design Automation and Test Europe, (DATE), Munich, Germany, Mar 2008
    • Miguel Miranda, "Variability Aware Timing/Energy Modeling of SoCs", tutorial at Design Automation and Test Europe, (DATE), Munich, Germany, Mar 2008


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.