Implementation of a coarse-grained reconfigurable media processor for AVC decoder

Journal of Signal Processing Systems

Volumn 51, Issue 3, 2008, Pages 225-243

  Mei, B ^a   De Sutter, B ^a   Vander Aa, T ^a   Wouters, M ^a   Kanstein, A ^b   Dupont, S ^a  

^a IMEC   (Belgium)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Embedded system; FPGA; H.264 AVC decoder; Multimedia; Reconfigurable architecture; VLIW

Indexed keywords

DECODING; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL LANGUAGES; MULTIMEDIA SYSTEMS; NETWORK ARCHITECTURE;

ARCHITECTURE FOR DYNAMICALLY RECONFIGURABLE EMBEDDED SYSTEMS (ADRES); AVC DECODER; COMPILATION TECHNIQUES;

DIGITAL SIGNAL PROCESSING;

EID: 43149106926     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-007-0152-8     Document Type: Article

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