Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008

Volumn , Issue , 2008, Pages 351-354

  Pak, Jun So ^a   Ryu, Chunghyun ^a   Kim, Jaemin ^a   Shim, Yujeong ^a   Kim, Gawon ^a   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; BONDING; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; DISTRIBUTED PARAMETER NETWORKS; DISTRIBUTION OF GOODS; ELECTRIC INVERTERS; ELECTRIC POWER DISTRIBUTION; ELECTROMAGNETIC COMPATIBILITY; ELECTROMAGNETISM; INDUCTANCE; MAGNETIC MATERIALS; RESONANCE; SILICA; SILICON; SILICON COMPOUNDS; SUBSTRATES;

CHIP DENSITIES; LOW POWERS; WIRE-BONDING;

ELECTRIC NETWORK ANALYSIS;

EID: 51749083076     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEMC.2008.4559884     Document Type: Conference Paper

References (4)

1. Sandra Winkler, Advanced IC Packaging, 2007 Edition, Electronic Trend Publications, 2007.
2. D. M. Jang, C. Ryu, K. Y. Lee, B. H. Cho, J. Kim, T. S. Oh, W. J. Lee, and J. Yu, "Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV)," Proc 2007 Elect. Comp. and Tech. Conf, Reno, Nevada, May. 2007, pp. 847-852.
3. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, " High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging", Electronics System-integration Technology Conf, vol 1, pp. 215-220, Sept. 2006.
4. st. 2007.