Symmetric and asymmetric double gate MOSFET modeling

Journal of Semiconductor Technology and Science

Volumn 9, Issue 4, 2009, Pages 225-232

  Abebe, H ^a   Cumberbatch, E ^b   Morris, H ^b   Tyree, V ^a   Numata, T ^c   Uno, S ^c  

^a University of Southern California   (United States)

^b CLAREMONT GRADUATE UNIVERSITY   (United States)

^c NAGOYA UNIVERSITY   (Japan)

Author keywords

Circuit simulation; Compact model; Device modeling; DG MOSFET

Indexed keywords

CIRCUIT SIMULATION;

CHANNEL CURRENTS; CHANNEL POTENTIAL; COMPACT MODEL; DEVICE MODELING; DG MOSFETS; DOUBLE GATE MOSFET; DOUBLE GATE MOSFET MODELS; LAMBERT FUNCTION;

MOSFET DEVICES;

EID: 73549105728     PISSN: 15981657     EISSN: None     Source Type: Journal    
DOI: 10.5573/JSTS.2009.9.4.225     Document Type: Article

References (15)

1. S. Adee, "Transistors go vertical," IEEE Spectrum, Nov., (2007).
2. H. Lu and Y. Taur, "Physics-Based, Non-Charge- Sheet Compact Modeling of Double Gate MOSFETs," Nanotech Proceedings, WCM, pp. 58-62, May 8-12, (2005), Anaheim, CA.
3. Y. Taur, X. Liang, W. Wang and H. Lu "A continuous, analytical drain-current model for double-gate MOSFETs," IEEE Electron Device Lett., Vol.25, pp. 107, Feb., (2004).
4. Y. Taur "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFET,"4 IEEE Trans. Electron Devices, Vol.48, pp.2861, Dec., (2001).
5. H. Abebe, H. Morris, E. Cumberbatch and V. Tyree, "Compact models for double gate MOSFET with quantum mechanical effects using Lambert function." Nanotech Proceedings, WCM, Vol.3, pp.849, June 1-5, (2008), Boston, Massachusetts, USA.
6. H. Morris, E. Cumberbatch, H. Abebe and V. Tyree, "Compact modeling for the I-V characteristics of double gate and surround gate MOSFETs," IEEE UGIM Proceedings, pp.117-121, June 25-28, (2006), San Jose, CA.
7. T. K Chiang, "A novel scaling-parameter-dependent subthreshold swing model for double-gate (DG) SOI MOSFETs: including effective conducting path effect (ECPE)" IOP Semicond. Sci. Technol. 19, pp. 1386-1390, (2004).
8. R. Corless, G. Gonnet, D. Hare, D. Jeffrey, and D. Knuth, "On the Lambert W function", Advances in Computational Mathematics 5(4): 329-359 (1996).
9. Sentaurus Device User Guide. Version Z-3.2007, March 2007, Synopsys.
10. Jin He, Feng Liu, Jian Zhang, Jie Feng, Jinhua Hu, Shengqi Yang, Mansun Chan, "A Carrier-Based Approach for Compact Modeling of the Long-Channel Undoped Symmetric Double-Gate MOSFETs," IEEE Transactions on Electron Devices, Vol.54, Issue. 5, pp1203-1209, May (2007).
11. A. Oritiz-Conde, F. J. Garcia Sonchez and S. Malobabic "Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETs," IEEE Trans. Electron Devices, Vol.52, pp.1669, Jul., (2005).
12. H. Lu and Y. Taur, "An analytic potential for asymmetric and symmetric Dg MOSFETs," IEEE Trans. Electron Devices, Vol.53, No.5, pp.1161-1168, May (2006).
13. A.S. Roy, C.C. Enz and J.M. Sallese, "A Charge-Based Compact Model of Double Gate MOSFET," Nanotech Proceedings, WCM, Vol.3, pp.662, June 1-5, (2006), Boston, Massachusetts, USA.
14. K. Chandrasekaran, Z.M. Zhu, X. Zhou, W. Shang-guan, G.H. See, S.B. Chiah, S.C. Rustagi and N. Singh, "Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach," Nanotech Proceedings, WCM, Vol.3, pp.792, June 1-5, (2006), Boston, Massachusetts, USA.
15. A. Oritiz-Conde, J. Garcia-Sanchez, Juan Muci, Slavica malobabic and Juin J. Lious, "A review of core compact models for undoped double-gate SOI MOSFETs," IEEE Tran. on Electron Devices, Vol. 54, No.1, January (2007).