An analytical performance model for the Spidergon NoC with virtual channels

Journal of Systems Architecture

Volumn 56, Issue 1, 2010, Pages 16-26

  Moadeli, Mahmoud ^a   Shahrabi, Alireza ^b   Vanderbauwhede, Wim ^a   Maji, Partha ^c  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b GLASGOW CALEDONIAN UNIVERSITY   (United Kingdom)

^c INSTITUTE FOR SYSTEM LEVEL INTEGRATION   (United Kingdom)

Author keywords

Network on Chip; Performance modelling; Spidergon; Virtual channels

Indexed keywords

ACCURATE ANALYSIS; ANALYTICAL MODEL; ANALYTICAL PERFORMANCE MODEL; COMMUNICATION INFRASTRUCTURE; DEGREE OF ACCURACY; FPGA IMPLEMENTATIONS; INTERCONNECT NETWORKS; MESSAGE LATENCY; MULTIPROCESSOR-SYSTEM; NETWORK ON CHIP; NETWORK THROUGHPUT; SIMULATION EXPERIMENTS; SOC APPLICATION; VIRTUAL CHANNELS; WORKING CONDITIONS;

COMPUTER SIMULATION; COST BENEFIT ANALYSIS; ELECTRIC NETWORK TOPOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); QUALITY OF SERVICE;

COMMUNICATION CHANNELS (INFORMATION THEORY);

EID: 73149117777     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2009.10.002     Document Type: Article

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