메뉴 건너뛰기




Volumn , Issue , 2007, Pages 76-

Communication modelling of the spidergon NoC with virtual channels

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY OF SERVICE;

EID: 47249125808     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2007.28     Document Type: Conference Paper
Times cited : (8)

References (18)
  • 1
    • 43949160401 scopus 로고
    • A comprehensive analytical model for wormhole routing in multicomputer systems
    • Nov
    • Jeffrey T. Draper , Joydeep Ghosh, "A comprehensive analytical model for wormhole routing in multicomputer systems", Journal of Parallel and Distributed Computing, v.23 n.2, p.202-214, Nov. 1994.
    • (1994) Journal of Parallel and Distributed Computing , vol.23 , Issue.2 , pp. 202-214
    • Draper, J.T.1    Ghosh, J.2
  • 5
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • Las Vegas, NV, USA, June
    • W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks", In Proceedings of the Design Automation Conference, pages 684-689, Las Vegas, NV, USA, June 2001.
    • (2001) Proceedings of the Design Automation Conference , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 6
    • 24144461667 scopus 로고    scopus 로고
    • Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
    • Partha Pratim Pande, Cristian Grecu, Michael Jones, Andre Ivanov, Resve Saleh, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures", IEEE Transactions on Computers, pp. 1025-1040, 2005.
    • (2005) IEEE Transactions on Computers , pp. 1025-1040
    • Pratim Pande, P.1    Grecu, C.2    Jones, M.3    Ivanov, A.4    Saleh, R.5
  • 7
    • 33645596737 scopus 로고
    • The Torus Routing Chip
    • Technical Report 5208:TR: 86, Computer Science Dept, California Inst. of Technology, pp
    • W.J. Dally and C.L. Seitz, "The Torus Routing Chip", Technical Report 5208:TR: 86, Computer Science Dept., California Inst. of Technology, pp. 1-19, 1986.
    • (1986) , pp. 1-19
    • Dally, W.J.1    Seitz, C.L.2
  • 8
    • 34548752803 scopus 로고    scopus 로고
    • A generic architecture for on-chip packet-switched interconnections
    • DAC, pp
    • P. Guerriert, A. Greiner, "A generic architecture for on-chip packet-switched interconnections", Proceedings of Design Automation Conference (DAC), pp 683-689, 2001.
    • (2001) Proceedings of Design Automation Conference , pp. 683-689
    • Guerriert, P.1    Greiner, A.2
  • 9
    • 84948696213 scopus 로고    scopus 로고
    • A network on chip architecture and design methodology
    • S. Kumar et al., "A network on chip architecture and design methodology", Proceedings of Int't Symp. VLSI (ISVLSI), pp. 117-124, 2002.
    • (2002) Proceedings of Int't Symp. VLSI (ISVLSI) , pp. 117-124
    • Kumar, S.1
  • 10
    • 0036760592 scopus 로고    scopus 로고
    • An Interconnection Architecture for Networking Systems on Chip
    • Sept./Oct
    • F. Karim et al., "An Interconnection Architecture for Networking Systems on Chip", IEEE Micro, vol. 22, no. 5 , pp. 36-45, Sept./Oct. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 36-45
    • Karim, F.1
  • 12
    • 21244433563 scopus 로고    scopus 로고
    • Spidergon: A novel on chip communication network
    • Tampere, Finland, Nov
    • M. Coppola et al. , "Spidergon: A novel on chip communication network", proc. Int'l Symposium on System on Chip 2004, Tampere, Finland, Nov 2004.
    • (2004) proc. Int'l Symposium on System on Chip
    • Coppola, M.1
  • 13
    • 0344286003 scopus 로고    scopus 로고
    • Message latency in the 2-dimensional mesh with wormhole routing
    • M. Ould-khaoua, "Message latency in the 2-dimensional mesh with wormhole routing", Microprocessors and Microsystems, 22(9):509-514, 1999.
    • (1999) Microprocessors and Microsystems , vol.22 , Issue.9 , pp. 509-514
    • Ould-khaoua, M.1
  • 15
    • 12444286718 scopus 로고    scopus 로고
    • Analysis of deterministic routing in k-ary n-cubes with virtual channels
    • H. Sarbazi-Azad, A. Khonsari, and M. Ould-Khaoua, "Analysis of deterministic routing in k-ary n-cubes with virtual channels," J. Interconnection Networks, vol.3, no.1-2, pp.85-101, 2002.
    • (2002) J. Interconnection Networks , vol.3 , Issue.1-2 , pp. 85-101
    • Sarbazi-Azad, H.1    Khonsari, A.2    Ould-Khaoua, M.3
  • 17
    • 34047104005 scopus 로고    scopus 로고
    • Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh
    • L. Bononi, N. Concer, "Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh", DATE, pp.154-159, 2006.
    • (2006) DATE , pp. 154-159
    • Bononi, L.1    Concer, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.