Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Solid-State Electronics

Volumn 49, Issue 3, 2005, Pages 377-383

  Park, Tai Su ^a   Choi, Siyoung ^b   Lee, Deok Hyung ^b   Chung, U In ^b   Moon, Joo Tae ^b   Yoon, Euijoon ^a   Lee, Jong Ho ^c  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Kyungpook National University   (South Korea)

Author keywords

Body tied; Bulk; DIBL; FinFET; MOSFET; Omega; SCE

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; DRY ETCHING; DYNAMIC RANDOM ACCESS STORAGE; FABRICATION; INSULATED GATE BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; MOSFET DEVICES; PHOTOLITHOGRAPHY; THICKNESS MEASUREMENT; VLSI CIRCUITS;

BODY-TIED; BULK; DIBL; FINFET; OMEGA; SCE;

SILICON WAFERS;

EID: 12344295893     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.10.001     Document Type: Article

References (10)

1. Kedzierski J, Nowak E, Kanarsky T, Zhang Y, Boyd D, Carruthers R, et al. Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation. In: IEEE International Electron Devices Meeting (IEDM), Technical Digest December; 2002. p. 247-50
2. Yu B, Chang L, Ahmed S, Wang H, Bell S, Yang C-Y, et al. 25 nm CMOS Omega FETs. In: IEEE International Electron Devices Meeting (IEDM), Technical Digest; December 2002. p. 251-4
3. C. Jean-Pierre Silicon-on-insulator technology: materials to VLSI 1991 Kluwer Academic Publishers
4. Yang F-L, Chen HY, Chen F-C, Huang C-C, Chang C-Y, Chiu H-K. FinFET process refinements for improved mobility and gate work function engineering. In: IEEE International Electron Devices Meeting (IEDM), Technical Digest; December 2002. p. 255-8
5. Park T, Choi S, Lee DH, Yoo JR, Lee BC, Kim JY, Lee CG, et al. Fabrication of body-tied FinFETS (Omega MOSFETs) using bulk si wafers. In: JSA P and IEEE Symposium on VLSI Technology, Kyoto, Japan, Technical Digest; June 2003. p. 135-6
6. 2 slurry and liner SiN as a CMP stopper. In: JSAP and IEEE Symposium on VLSI Technology, Technical Digest; June 1999. p. 159-60
7. Jeong HS. Highly manufacturable 4 Gb DRAM using 0.11 μm DRAM Technology. In: IEEE Electron Devices Meeting (IEDM), Technical Digest; December 2000. p. 353-356
8. Kao D-B, McVittie JP, Nix WD, Saraswat KC. Two-dimensional silicon oxidation experiments and theory. In: IEEE International Electron Devices Meeting (IEDM), Technical Digest; December 1985. p. 388-91
9. Tai-su Park, Euijoon Yoon, Jong-Ho Lee. A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer, IEE Phys E2003;19(1):6-12
10. Lim H-K, Fossum JG. Threshold voltage of thin film silicon on insulator (SOI) MOSFET's, IEEE Trans Electron Dev 1983;30:1244-51