A 40 Gb/s multi-data-rate CMOS transmitter and receiver chipset with SFI-5 interface for optical transmission systems

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3568-3579

  Kaeriyama, Shunichi ^a   Amamiya, Yasushi ^a   Noguchi, Hidemi ^a   Yamazaki, Zin ^a   Yamase, Tomoyuki ^a   Hosoya, Kenichi ^a   Okamoto, Minoru ^a   Tomari, Shiro ^a   Yamaguchi, Hiroshi ^a   Shoda, Hiroaki ^a   Ikeda, Hironobu ^a   Tanaka, Shinji ^a   Takahashi, Tsugio ^a   Ohhira, Risato ^a   Noda, Arihide ^a   Hijioka, Ken'ichiro ^b   Tanabe, Akira ^b   Fujita, Sadao ^a   Kawahara, Nobuhiro ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

40 Gb s; Clock and data recovery (CDR); Clock multiplication unit (CMU); OC 768; OTU 3; SerDes; SFI 5; STM 256

Indexed keywords

40 GB/S; 65NM CMOS TECHNOLOGY; BGA PACKAGE; CHIPSET; CLOCK AND DATA RECOVERY; CLOCK AND DATA RECOVERY (CDR); CMOS TECHNOLOGY; CMOS TRANSMITTERS; CONTROL INTERFACES; DATA-RATE; DUTY CYCLES; FULL INTEGRATION; FULL-RATE CLOCK ARCHITECTURE; FULLY INTEGRATED; JITTER PERFORMANCE; LOW-POWER CONSUMPTION; OPTICAL TRANSMISSION SYSTEMS; PRBS PATTERN; TRANSMITTER AND RECEIVER;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER TRANSMISSION; INSTRUMENT SCALES; LIGHT TRANSMISSION; PHASE LOCKED LOOPS; TIMING JITTER; TRANSMITTERS;

CLOCKS;

EID: 72949106316     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2031026     Document Type: Conference Paper

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