A 39.8Gb/s to 43.1Gb/s SFI-5 compliant 16:1 multiplexer and 1:16 demultiplexer for optical communication systems

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 581-584

  Krawczyk, Thomas W ^a   Steidl, Samuel A ^a   Alexander, Richard ^a   Pulver, James ^a   Kowalski, Gary ^a   Hornbuckle, Craig ^a   Rowe, David ^a  

^a Sierra Monolithics Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; ELECTRIC POTENTIAL; OPTICAL COMMUNICATION; OPTICAL LINKS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY ARRAY; CLOCK MULTIPLIER UNIT; DEMULTIPLEXER; PSEUDO-RANDOM BIT SEQUENCE GENERATOR;

MULTIPLEXING EQUIPMENT;

EID: 0242443642     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A. Joseph, et al., "A 0.18 m BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC-compatible CMOS using copper interconnect," Proc. IEEE BCTM, pp. 143-146, 2001.
2. Peter Dartnell, et al., "Serdes framer interface level 5 (SFI-5): implementation agreement for 40Gb/s interface for physical layer devices," Implementation Agreement OIF-SF15-01.0 Optical Internet-working Forum, Jan. 29, 2002.
3. R. C. Walker, et al., "A 2.488Gb/s Si Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection," ISSCC Dig. Tech Papers, pp. 246-247, Feb. 1997.
4. Adrian Ong, et al., "A 40-43Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology," ISSCC Dig. Tech. Papers, pp. 234-235, Feb., 2003.
5. Derek K. Shaeffer, et al., "A 40/43Gb/s SONET OC-768 SiGe 4:1 MUX/CMU," ISSCC Dig. Tech. Papers, pp. 236-237, Feb., 2003.
6. Min Xu, et al., "An SFI-5 compliant 16:4 multiplexer for OC-768 systems," ISSCC Dig. Tech. Papers, pp. 238-239, 490, Feb., 2003.
7. Akio Koyama, et al., "43Gb/s full-rate-clock 16:1 multiplexer and 1:16 demultiplexer with SFI-5 interface in SiGe BiCMOS technology," ISSCC Dig. Tech. Papers, pp. 232-233, 490, Feb.
8. Mounir Meghelli, et al., "A 0.18μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems," ISSCC Dig. Tech. Papers, pp. 230-231, 490, Feb., 2003.
9. Jeffrey Yen, et al., "A fully integrated 43.2Gb/s clock and data recovery and 1:4 demux IC in InP HBT technology," ISSCC Dig. Tech. Papers, pp. 240-241, 491, Feb., 2003.