A 40-Gb/s transceiver in 0.13-μm CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 196-197

  Kim, Jeong Kyoum ^a   Kim, Jaeha ^c   Kim, Gyudong ^b   Chi, Hankyu ^a   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

^b Silicon Image Inc   (United States)

^c RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BALL GRID ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; JITTER; PHASE COMPARATORS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS; VLSI CIRCUITS;

BANG-BANG PHASE DETECTORS; CLOCK-JITTER; CMOS TECHNOLOGY; FULLY INTEGRATED; PLASTIC BALL GRID ARRAYS;

EQUALIZERS;

EID: 51949103649     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586004     Document Type: Conference Paper

References (4)

1. J. Kim, et al., "Circuit Techniques for a 40Gb/s Transmitter in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 150-151, Feb., 2005.
2. J. Kim, et al., "A 20-GHz Phase-Locked Loop for 40-Gb/s Serializing Transmitter in 0.13-μm CMOS," J. Solid State Circuits, pp.899-908, Apr., 2006.
3. A. Ong, et al., "A 40-43-Gb/s Clock and Data Recovery IC with Integrated SFI-5 1:16 Demultiplexer in SiGe Technology," J. Solid-State Circuits, pp. 2155-2168, Dec., 2003.
4. D. K. Shaeffer and S. Kudszus, "Performance-Optimized Microstrip Coupled VCOs for 40-GHz and 43-GHz OC-768 Optical Transmission," J. Solid-State Circuits, pp. 1130-1138, July, 2003.