A 35-to-46-Gb/s ultra-low jitter clock and data recovery circuit for optical fiber transmission systems

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

Volumn , Issue , 2007, Pages 147-150

  Noguchi, Hidemi ^a   Hosoya, Kenichi ^a   Ohhira, Risato ^a   Uchida, Hiroaki ^a   Noda, Arihide ^a   Yoshida, Nobuhide ^a   Wada, Shigeki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Clock and data recovery (CDR); InP HBT; LC VCO; Optical fiber transmission

Indexed keywords

COMPOUND SEMICONDUCTOR (CS); FREQUENCY TRACKING; INP-HBT; LOW JITTER CLOCK; LOW JITTERS; OPTICAL FIBER TRANSMISSION SYSTEMS; PHASE TRACKING LOOPS; ULTRA-WIDE;

EID: 47349105082     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS07.2007.40     Document Type: Conference Paper

References (3)

1. H.Noguchi et al., "A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 252-253.
2. H.Nosaka et al., "A 39-to-45-Gbit/s Multi-Data-Rate Clock and Data Recovery Circuit With a Robust Lock Detector," IEEE J. Solid-State Circuits, vol. 39, No.8, pp. 1361-1365, August 2004.
3. M.Meghelli et al., "A 0.18-μm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems," IEEE J. Solid-State Circuits, vol. 38, No.12, pp. 2147-2154, December 2003