A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Watanabe, Keiki ^a,e   Koyama, Akio ^a   Harada, Takashi ^a   Aida, Tatsuhiro ^a   Ito, Atsushi ^a   Murata, Tomoo ^a   Yoshioka, Hiroyuki ^a   Sonehara, Masahito ^a   Yamashita, Hiroki ^b   Ishikawa, Kyosuke ^b   Ito, Masahiro ^b   Shiramizu, Nobuhiro ^b   Nakamura, Takahiro ^b   Ohhata, Kenichi ^c   Arakawa, Fumihiko ^c   Kusunoki, Takeshi ^c   Chiba, Hiroyuki ^d   Kurihara, Tsutomu ^d   Kuraishi, Mamoru ^d  

^a Device Development Center   (Japan)

^b Central Research Laboratory   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

^d HITACHI LTD   (Japan)

^e NONE

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK DIAGRAMS; POWER DISSIPATION;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; DATA REDUCTION; ELECTRIC CURRENTS; JITTER; NATURAL FREQUENCIES; SEMICONDUCTING SILICON COMPOUNDS; VARACTORS;

MICROPROCESSOR CHIPS;

EID: 2442707643     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A. Ong, et al., "A 40-43Gb/s Clock and Data Recovery IC with Integrated SFI-5 1:16 Demultiplexer in SiGe Technology," ISSCC Dig. Tech. Papers, pp. 234-235, Feb. 2008.
2. D. Shaeffer, et al., "A40/43Gb/s SONET OC-768 SiGe 4:1 MUX/CMU," ISSCC Dig. Tech. Papers, pp. 236-237, Feb. 2003.
3. Optical Internetworking Forum Document, "Implementation Agreement OIF-SFI5-01.0," Jan. 2002.
4. A. Koyama, et al., "43Gb/s Full-Rate-Clock 16:1 Multiplexer and 1:16 Demultiplexer with SFI-5 Interface in SiGe BiCMOS Technology," ISSCC Dig. Tech. Papers, pp. 232-233, Feb. 2003.
5. ITU-T G.8251, "The Control of Jitter and Wander Within the Optical Transport Network," Oct. 2001.