Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 27, Issue 6, 2009, Pages 2790-2794

  Wang, Chao ^a   Chou, Stephen Y ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALIGNMENT ACCURACY; ETCHING MASKS; FABRICATION METHOD; OVERLAY ALIGNMENT; SELF-ALIGNED; SHADOW EVAPORATION; SI/SIGE HETEROJUNCTION; SOURCE REGION; SOURCE/DRAIN STRUCTURES; STRINGENT REQUIREMENT; TUNNELING FIELD-EFFECT TRANSISTORS;

ALIGNMENT; EVAPORATION; FABRICATION; HETEROJUNCTIONS; REACTIVE ION ETCHING; TUNNELING (EXCAVATION); VAPORS; WIND TUNNELS;

FIELD EFFECT TRANSISTORS;

EID: 72849124050     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.3237138     Document Type: Conference Paper

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