Error-resilient low-power viterbi decoder architectures

IEEE Transactions on Signal Processing

Volumn 57, Issue 12, 2009, Pages 4906-4917

  Abdallah, Rami A ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Algorithmic noise tolerance; Error resiliency; Process variations; Viterbi decoder (VD); Voltage overscaling

Indexed keywords

ALGORITHMIC NOISE TOLERANCES; ERROR RESILIENCY; PROCESS VARIATION; VITERBI DECODER; VOLTAGE OVERSCALING;

BIT ERROR RATE; CODING ERRORS; DESIGN; ERROR CORRECTION; INTEGRATED CIRCUIT TESTING; SIGNAL TO NOISE RATIO; TIME MEASUREMENT; VITERBI ALGORITHM;

DECODING;

EID: 70450250129     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2009.2026078     Document Type: Article

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