Impact of Cu/low-k interconnect design on chip package interaction in flip chip package

AIP Conference Proceedings

Volumn 1143, Issue , 2009, Pages 185-196

  Uchibori, C J ^a   Lee, Michael ^a   Zhang, Xuefeng ^b   Ho, P S ^b   Nakamurac, T ^c  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70450247343     PISSN: 0094243X     EISSN: 15517616     Source Type: Conference Proceeding    
DOI: 10.1063/1.3169258     Document Type: Conference Paper

References (14)

1. D. Edelstein, et. al., "Full Copper Wiring in a sub-0.25μm CMOS ULSI Technology",Electron Dev. Meeting, pp. 773-776, Dec 1997 [Int. Technical Digest, 1997].
2. S. Venkatesan, et. al., "A High Performance 1.8V, 0.2μm CMOS Technology with Copper Metallization", Electron Dev. Meeting, pp. 769-772, Dec 1997 [Int. Technical Digest, 1997].
3. N. Aoi, T. Fukuda and H. Yanazawa, "Evaluation and Analysis for Mechanical Strengths of Low k Dielectrics by a Finite Element Method", in Proc. IEEE 2002 Int. Interconnect Technol. Conf., 2002, pp. 72-74.
4. L. L. Mercado, C. Goldberg, S-M. Kuo, T-Y. T. Lee and S. Pozder, "Analysis of Flip-Chip Packaging Challenges on Copper Low-k Interconnects", in Proc. 53th Electronic Components and Technol. Conf., 2003, pp. 1784-1790.
5. Lei L. Mercado, S-M. Kuo, C. Goldberg and D. Frear, "Impact of Flip-Chip Packaging on Copper/Low-k Structures", IEEE Trans. Adv. Packaging, vol. 26, pp. 433-440, November 2003.
6. G. Wang, C. Merrill, J-H Zhao, S. K. Groothuis and P. S. Ho, "Packaging effects on reliability of Cu/low-k interconnects", IEEE Trans. Dev. and Mat. Reliability, vol. 2, pp. 119-128, Dec. 2003.
7. C. J. Zhai, et. al., "Investigation of Cu/Low-k Film Delamination in Flip Chip Packages", in Proc. 56th Electronic Components and Technol. Conf., 2006, pp. 709-717.
8. G. T. Wang, X. F. Zhang and P. S. Ho, "Chip-Packaging Interaction and Reliability Impact on Cu/Low k Interconnects", in Proc. Inter. Stress Workshop, AIP Conf. Proc. Series, Vol. 817, 2005, pp.73-82
9. C. J. Uchibori, Xuefeng Zhang, P. S. Ho and T. Nakamura, "Effects of Chip-Package Interaction on Mechanical Reliability of Cu Interconnects for 65nm Technology Node and Beyond", in Proc. IEEE Int. Interconnect Tech. Conf., 2006, pp. 196-198.
10. Chihiro. J. Uchibori, Xuefeng Zhang, P. S. Ho and T. Nakamura, "Investigation of Interconnect Design on Chip Package Interaction and Mechanical Reliability of Cu/Low-k Multi-Layer Interconnects in Flip Chip Package", in Proc. IEEE Int. Interconnect Tech. Conf., 2008, pp. 150-152.
11. th International Workshop on Stress-Induced Phenomena in Metallization, 2007, pp. 170-179.
12. J. Liang, R. Huang, J. H. Prevost and Z. Suo, "Thin Film Cracking Modulated by Underlayer Creep", Experiment. Mechanics, 43, 2003, pp. 269-279.
13. th Inter. Stress Workshop, AIP Conf. Proc. Vo l 741, p3, 2004.
14. E. Suhir, "Interfacial Stresses in Bimetal Thermostats", J. Appl. Mech., 595-600, 56 (1989).