Effects of chip-package interaction on mechanical reliability of Cu interconnects for 65nm technology node and beyond

2006 International Interconnect Technology Conference, IITC

Volumn , Issue , 2006, Pages 196-198

  Uchibori, Chihiro J ^a   Zhang, Xuefeng ^b   Ho, Paul S ^b   Nakamura, Tomoji ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRAZING; CHEMICAL VAPOR DEPOSITION; CHIP SCALE PACKAGES; COPPER; COPPER ALLOYS; DIES; ELECTROMAGNETIC WAVE PROPAGATION; ELECTRONIC EQUIPMENT MANUFACTURE; FLOW INTERACTIONS; LEAD; NANOTECHNOLOGY; OPTICAL INTERCONNECTS; SOLDERING ALLOYS; TECHNOLOGY; THERMOANALYSIS; THREE DIMENSIONAL; WELDING;

65-NM NODES; 65NM TECHNOLOGY; CHIP-PACKAGE INTERACTION; CU INTERCONNECTS; DIE ATTACH PROCESS; HIGH THERMAL; INTERCONNECT RELIABILITY; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; LOW-K INTERCONNECTS; MATE RIAL PROPERTIES; MECHANICAL RELIABILITY; MULTI-LEVEL; PB-FREE SOLDERS; POROUS MSQ; SOLDER REFLOWING; SPIN-ON POLYMER; SUB-MODELING METHOD; UNDERFILLING;

MECHANICAL PROPERTIES;

EID: 41749124022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2006.1648686     Document Type: Conference Paper

References (13)

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