Novel fault-tolerant adder design for FPGA-based systems

Proceedings - 7th International On-Line Testing Workshop, IOLTW 2001

Volumn 2001-January, Issue , 2001, Pages 54-58

  Alderighi, Monica ^a   D'Angelo, Sergio ^a   Metra, Cecilia ^b   Sechi, Giacomo R ^a  

^a Istituto di Fisica Cosmica G Occhialini   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; FAULT TOLERANCE; INTEGRATED CIRCUIT DESIGN;

CONVENTIONAL DESIGN; DEPENDABLE SYSTEMS; DESIGN COSTS; FAULT TOLERANT ADDER; FIELD PROGRAMMABLE GATE ARRAY (FPGAS); POST LAYOUT SIMULATION; VERY DEEP SUB-MICRON TECHNOLOGIES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70449703402     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2001.937819     Document Type: Conference Paper

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