Design verification of FPGA implementations

IEEE Design and Test of Computers

Volumn 16, Issue 2, 1999, Pages 66-73

  Chen, Xiao Tao ^a   Huang, Wei Kang ^a   Park, Nohpill ^b   Meyer, Fred J ^c   Lombardi, Fabrizio ^d  

^a FUDAN UNIVERSITY   (China)

^b Samsung SDS   (South Korea)

^c Northeastern University   (United States)

^d Northeastern University ^*

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

AUTOMATIC TEST PATTERN GENERATION (ATPG);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033115128     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.765205     Document Type: Article

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