Ratioed voter circuit for testing and fault-tolerance in vlsi processing arrays

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 43, Issue 2, 1996, Pages 143-152

  Belabbes, Nacer Eddine ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC INVERTERS; ERROR DETECTION; INTERCONNECTION NETWORKS; MOS DEVICES; SENSITIVITY ANALYSIS; TRANSISTORS; ULSI CIRCUITS; VLSI CIRCUITS; WSI CIRCUITS;

EQUIVALENT CAPACITANCE; INTERCONNECTION CAPACITANCE; TRIPLE MODULAR REDUNDANCY;

INTEGRATED CIRCUIT TESTING;

EID: 0030086112     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.486436     Document Type: Article

References (13)

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2. Dynamic triple modular redundancy (DTMR): A novel testing technique for fault-tolerant processor arrays in 1m. Workshop Defect and Fault Tolerance VLSI Syst./IFIP-IEEE Grenoble/France 1990 pp. 289-298.
3. A. Guterman Y. Savaria and M. Dagenais Dynamic N-modular redundancy (DNMR): A unified approach for testing and reconfiguration of fault-tolerant processor arrays in 6th Wkshp. New Directions in Testing Montréal/Canada. 1992. pp. 251-261.
4. A. Guterman Approche unifiée pour le test et la reconfiguration des matrices de processeurs tolérantes aux pannes Ph.D. dissertation École Polytech. Montréal Départ. Génie Électrique et de Génie Inform. 1992.
5. A. Mukherjee Introduction to NMOS and CMOS VLSI Systems Design. Englewood Cliffs NJ: Prentice Hall 1986.
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8. N. Belabbes A. Guterman Y. Savaria and M. Dagenais Ralioed voter circuit for testing and fault-tolerance in VLSI processing arrays in lSCAS-92 San Diego/USA 1992.
9. N. Belabbes Étude et réalisation d'un voleur DNMR pour les tests concurrents M.Sc.A. Thesis École Polytech. Montréal Départ. Génie Électrique et de Génie Inform. 1992.
10. N. H. E. Weste and K. Eshraghian Principles of CMOS VLSI Design - A Systems Perspective Appendix. Reading MA: Addison-Wesley 1985.
11. A. Guterman Y. Savaria and M. Dagenais On the diagnusabiliry of DNMR testing presented at European Test Conf./ETC-93 1993.
12. Canadian Microelectron. Corp. Design Rules and Process Parameters for the Northern Telecom CMOS3dlm and CMOS4S Processes.
13. HSPICE H8801 User's Manual Meta-Software Inc Campbell CA 95008. (1988).